Datasheet InnoSwitch3-CE (Power Integrations) - 8

InnoSwitch3-CE SR Disable Protection Intelligent Quasi-Resonant Mode Switching
In each cycle SR is only engaged if a set cycle was requested by the In order to improve conversion efficiency and reduce switching secondary control er and the negative edge is detected on the losses, the InnoSwitch3-CE features a means to force switching when FORWARD pin. In the event that the voltage on the ISENSE pin the voltage across the primary switch is near its minimum voltage exceeds approximately 3 times the CC threshold, the SR FET drive is when the converter operates in discontinuous conduction mode (DCM). disabled until the surge current has diminished to nominal levels. This mode of operation is automatical y engaged in DCM and disabled
SR Static Pull-Down
once the converter moves to continuous-conduction mode (CCM). To ensure that the SR gate is held low when the secondary is not in Rather than detecting the magnetizing ring val ey on the primary- control, the SYNCHRONOUS RECTIFIER DRIVE pin has a nominal y side, the peak voltage of the FORWARD pin voltage as it rises above “ON” device to pull the pin low and reduce any voltage on the SR gate the output voltage level is used to gate secondary requests to initiate due to capacitive coupling from the FORWARD pin. the switch “ON” cycle in the primary control er.
Open SR Protection
The secondary control er detects when the control er enters in In order to protect against an open SYNCHRONOUS RECTIFIER discontinuous-mode and opens secondary cycle request windows DRIVE pin system fault the secondary control er has a protection corresponding to minimum switching voltage across the primary mode to ensure the SYNCHRONOUS RECTIFIER DRIVE pin is power MOSFET. connected to an external FET. If the external capacitance on the SYNCHRONOUS RECTIFIER DRIVE pin is below 100 pF, the device Quasi-Resonant (QR) mode is enabled for 20 ms after DCM is detected will assume the SYNCHRONOUS RECTIFIER DRIVE pin is “open” and or when ring amplitude (pk-pk) >2 V. Afterwards, QR switching is there is no FET to drive. If the pin capacitance detected is above disabled, at which point switching may occur at any time a secondary 100 pF, the control er will assume an SR FET is connected. request is initiated. In the event the SYNCHRONOUS RECTIFIER DRIVE pin is detected to The secondary control er includes blanking of ~1 ms to prevent false be open, the secondary control er will stop requesting pulses from detection of primary “ON” cycle when the FORWARD pin rings below the primary to initiate auto-restart. ground. See Figure 9. If the SYNCHRONOUS RECTIFIER DRIVE pin is tied to ground at start-up, the SR drive function is disabled and the open SYNCHRONOUS RECTIFIER DRIVE pin protection mode is also disabled.
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Rev. D 08/18 www.power.com Document Outline Product Highlights Description Output Power Table Pin Functional Description InnoSwitch3-CE Functional Description Primary Controller Secondary Controller Applications Example Key Application Considerations Selection of Components Recommendations for Circuit Board Layout Layout Example Quick Design Checklist Absolute Maximum Ratings Thermal Resistance Key Electrical Characteristics Typical Performance Curves InSOP-24D Package Drawing InSOP-24D Package Marking Part Ordering Table MSL Table ESD and Latch-Up Table Part Ordering Information