Datasheet InnoSwitch3-CE (Power Integrations) - 6

FabricantePower Integrations
DescripciónOff-Line CV/CC QR Flyback Switcher IC with Integrated 650 V MOSFET, Synchronous Rectification & FluxLink Feedback for Applications up to 65 W
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InnoSwitch3-CE. Maximum Switching Frequency. Frequency Soft-Start. Wait and Listen. Audible Noise Reduction Engine

InnoSwitch3-CE Maximum Switching Frequency Frequency Soft-Start Wait and Listen Audible Noise Reduction Engine

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InnoSwitch3-CE
The most likely event that could require an additional handshake is cycle requests is limited by a minimum cycle off-time of t . OFF(MIN) when the primary stops switching as the result of a momentary line This is in order to ensure that there is sufficient reset time after brown-out event. When the primary resumes operation, it will default primary conduction to deliver energy to the load. to a start-up condition and attempt to detect handshake pulses from
Maximum Switching Frequency
the secondary. The maximum switch-request frequency of the secondary control er If the secondary does not detect that the primary responds to is f . SREQ switching requests for 8 consecutive cycles, or if the secondary
Frequency Soft-Start
detects that the primary is switching without cycle requests for 4 or At start-up the primary control er is limited to a maximum switching more consecutive cycles, the secondary control er will initiate a frequency of f and 75% of the maximum programmed current limit second handshake sequence. This provides additional protection SW at the switch-request frequency of 100 kHz. against cross-conduction of the SR FET while the primary is switching. This protection mode also prevents an output overvoltage The secondary control er temporarily inhibits the FEEDBACK short condition in the event that the primary is reset while the secondary is protection threshold (V ) until the end of the soft-start (t ) FB(OFF) SS(RAMP) still in control. time. After hand-shake is completed the secondary control er linearly ramps up the switching frequency from f to f over the t
Wait and Listen
SW SREQ SS(RAMP) time period. When the primary resumes switching after initial power-up recovery from an input line voltage fault (UV or OV) or an auto-restart event, it In the event of a short-circuit or overload at start-up, the device will will assume control and require a successful handshake to relinquish move directly into CC (constant-current) mode. The device will go control to the secondary control er. into auto-restart (AR), if the output voltage does not rise above the V threshold before the expiration of the soft-start timer (t ) As an additional safety measure the primary will pause for an FB(AR) SS(RAMP) after handshake has occurred. auto-restart on-time period, t (~82 ms), before switching. During AR this “wait” time, the primary will “listen” for secondary requests. If it The secondary control er enables the FEEDBACK pin-short protection sees two consecutive secondary requests, separated by ~30 ms, the mode (V ) at the end of the t time period. If the output FB(OFF) SS(RAMP) primary will infer secondary control and begin switching in slave short maintains the FEEDBACK pin below the short-circuit threshold, mode. If no pulses occurs during the t “wait” period, the primary the secondary will stop requesting pulses triggering an auto-restart AR will begin switching under primary control until handshake pulses are cycle. received. If the output voltage reaches regulation within the t time
Audible Noise Reduction Engine
SS(RAMP) period, the frequency ramp is immediately aborted and the secondary The InnoSwitch3-CE features an active audible noise reduction mode control er is permitted to go full frequency. This will al ow the whereby the control er (via a “frequency skipping” mode of operation) control er to maintain regulation in the event of a sudden transient avoids the resonant band (where the mechanical structure of the loading soon after regulation is achieved. The frequency ramp will power supply is most likely to resonate − increasing noise amplitude) only be aborted if quasi-resonant-detection programming has already between 7 kHz and 12 kHz - 143 ms and 83 ms. If a secondary occurred. control er switch request occurs within this time window from the last conduction cycle, the gate drive to the power MOSFET is inhibited.
Maximum Secondary Inhibit Period
Secondary requests to initiate primary switching are inhibited to
Secondary Controller
maintain operation below maximum frequency and ensure minimum As shown in the block diagram in Figure 4, the IC is powered by a off-time. Besides these constraints, secondary-cycle requests are 4.4 V (V ) regulator which is supplied by either VOUT or FWD. The also inhibited during the “ON” time cycle of the primary switch (time BPS SECONDARY BYPASS pin is connected to an external decoupling between the cycle request and detection of FORWARD pin falling capacitor and fed internal y from the regulator block. edge). The maximum time-out in the event that a FORWARD pin falling edge is not detected after a cycle requested is ~30 ms. The FORWARD pin also connects to the negative edge detection
Output Voltage Protection
block used for both handshaking and timing to turn on the SR FET In the event that the sensed voltage on the FEEDBACK pin is 2% connected to the SYNCHRONOUS RECTIFIER DRIVE pin. The higher than the regulation threshold, a bleed current of ~2.5 mA (3 FORWARD pin voltage is used to determine when to turn off the mA max) is applied on the OUTPUT VOLTAGE pin (weak bleed). This SR FET in discontinuous conduction mode operation. This is when bleed current increases to ~200 mA (strong bleed) in the event that the voltage across the R of the SR FET drops below zero volts. DS(ON) the FEEDBACK pin voltage is raised beyond ~10% of the internal In continuous conduction mode (CCM) the SR FET is turned off when FEEDBACK pin reference voltage. The current sink on the OUTPUT the feedback pulse is sent to the primary to demand the next VOLTAGE pin is intended to discharge the output voltage after switching cycle, providing excel ent synchronous operation, free of momentary overshoot events. The secondary does not relinquish any overlap for the FET turn-off. control to the primary during this mode of operation. The mid-point of an external resistor divider network between the If the voltage on the FEEDBACK pin is sensed to be 20% higher than OUTPUT VOLTAGE and SECONDARY GROUND pins is tied to the the regulation threshold, a command is sent to the primary to either FEEDBACK pin to regulate the output voltage. The internal voltage latch-off or begin an auto-restart sequence (see Secondary Fault comparator reference voltage is V (1.265 V). Response in Feature Code Addendum). This integrated V OVP can FB OUT be used independently from the primary sensed OVP or in conjunction. The external current sense resistor connected between ISENSE and SECONDARY GROUND pins is used to regulate the output current in
FEEDBACK Pin Short Detection
constant current regulation mode. If the sensed FEEDBACK pin voltage is below V at start-up, the FB(OFF) secondary control er will complete the handshake to take control of
Minimum Off-Time
the primary complete t and will stop requesting cycles to initiate The secondary control er initiates a cycle request using the inductive- SS(RAMP) auto-restart (no cycle requests made to primary for longer than t connection to the primary. The maximum frequency of secondary- AR(SK) second triggers auto-restart).
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Rev. D 08/18 www.power.com Document Outline Product Highlights Description Output Power Table Pin Functional Description InnoSwitch3-CE Functional Description Primary Controller Secondary Controller Applications Example Key Application Considerations Selection of Components Recommendations for Circuit Board Layout Layout Example Quick Design Checklist Absolute Maximum Ratings Thermal Resistance Key Electrical Characteristics Typical Performance Curves InSOP-24D Package Drawing InSOP-24D Package Marking Part Ordering Table MSL Table ESD and Latch-Up Table Part Ordering Information