Datasheet ADL5240 (Analog Devices) - 2
| Fabricante | Analog Devices |
| Descripción | 100 MHz TO 4000 MHz RF/IF Digitally Controlled VGA |
| Páginas / Página | 28 / 2 — ADL5240. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 6/13—Rev. 0 to … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 1.2 Mb |
| Idioma del documento | Inglés |
ADL5240. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY. 6/13—Rev. 0 to Rev. A. 7/11—Revision 0: Initial Version
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ADL5240 Data Sheet TABLE OF CONTENTS
Features .. 1 Applications Information .. 16 Applications ... 1 Basic Layout Connections ... 16 General Description ... 1 SPI Timing... 18 Functional Block Diagram .. 1 Loop Performance .. 20 Revision History ... 2 Amplifier Drive Level for Optimum ACLR .. 22 Specifications ... 3 Thermal Considerations .. 22 Absolute Maximum Ratings .. 8 Evaluation Board .. 23 ESD Caution .. 8 Outline Dimensions ... 28 Pin Configuration and Function Descriptions ... 9 Ordering Guide .. 28 Typical Performance Characteristics ... 10
REVISION HISTORY 6/13—Rev. 0 to Rev. A
Changes to Table 1 ... 4 Changes to Table 3 ... 9 Changes to Figure 3 ... 11 Changes to Figure 16 ... 12 Added Figure 29, Renumbered Sequentially ... 14 Changes to Table 5, Figure 35, and Figure 36 .. 18 Added Amplifier Drive Level for Optimum ACLR Section and Figure 39 .. 22 Changes to Evaluation Board Section ... 23 Changes to Figure 41 and Table 8 .. 24 Added Figure 42 ... 25 Changes to Figure 43 and Figure 44 .. 26 Added Figure 45 ... 27
7/11—Revision 0: Initial Version
Rev. A | Page 2 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Applications Information Basic Layout Connections Amplifier Bias Digital Step Attenuator Bias Amplifier RF Input Interface Amplifier RF Output Interface DSA RF Input Interface DSA RF Output Interface DSA SPI Interface SPI Timing SPI Timing Sequence Loop Performance Amplifier Drive Level for Optimum ACLR Thermal Considerations Evaluation Board Outline Dimensions Ordering Guide
ADL5240 Data Sheet TABLE OF CONTENTS
Features .. 1 Applications Information .. 16 Applications ... 1 Basic Layout Connections ... 16 General Description ... 1 SPI Timing... 18 Functional Block Diagram .. 1 Loop Performance .. 20 Revision History ... 2 Amplifier Drive Level for Optimum ACLR .. 22 Specifications ... 3 Thermal Considerations .. 22 Absolute Maximum Ratings .. 8 Evaluation Board .. 23 ESD Caution .. 8 Outline Dimensions ... 28 Pin Configuration and Function Descriptions ... 9 Ordering Guide .. 28 Typical Performance Characteristics ... 10
REVISION HISTORY 6/13—Rev. 0 to Rev. A
Changes to Table 1 ... 4 Changes to Table 3 ... 9 Changes to Figure 3 ... 11 Changes to Figure 16 ... 12 Added Figure 29, Renumbered Sequentially ... 14 Changes to Table 5, Figure 35, and Figure 36 .. 18 Added Amplifier Drive Level for Optimum ACLR Section and Figure 39 .. 22 Changes to Evaluation Board Section ... 23 Changes to Figure 41 and Table 8 .. 24 Added Figure 42 ... 25 Changes to Figure 43 and Figure 44 .. 26 Added Figure 45 ... 27
7/11—Revision 0: Initial Version
Rev. A | Page 2 of 28 Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Applications Information Basic Layout Connections Amplifier Bias Digital Step Attenuator Bias Amplifier RF Input Interface Amplifier RF Output Interface DSA RF Input Interface DSA RF Output Interface DSA SPI Interface SPI Timing SPI Timing Sequence Loop Performance Amplifier Drive Level for Optimum ACLR Thermal Considerations Evaluation Board Outline Dimensions Ordering Guide