Datasheet ADL5201 (Analog Devices) - 6

ADL5201 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS S S S S P U O O O O P P P P M W V V V V P P 4 3 2 1 0 2 2 2 2 9 2 1 GND 1 18 VPOS VIN+ 2 17 VOUT– VIN– 3 ADL5201 16 VOUT+ GND 4 TOP VIEW 15 VOUT– (Not to Scale) MODE1 5 14 VOUT+ MODE0 6 13 LATCH 7 8 9 01 11 21 5 4 3 2 1 0 A A / / A/ A/ A/ A/ O K S A K T I L C F L A D C / /0 C D S S 1 S S _ _ G G N N D D P P U U NOTES 1. THE EXPOSED PADDLE (EP) MUST BE CONNECTED TO
004
A LOW IMPEDANCE GROUND PAD.
09388- Figure 5. Pin Configuration
Table 3. Pin Function Descriptions Pin No. Mnemonic Description
1, 4, EP GND Ground. The exposed paddle (EP) must be connected to a low impedance ground pad. 2 VIN+ Positive Input. 3 VIN− Negative Input. 5 MODE1 MSB for Mode Control. With the MODE0 pin, selects parallel, SPI, or up/down interface mode. 6 MODE0 LSB for Mode Control. With the MODE1 pin, selects parallel, SPI, or up/down interface mode. 7 SDIO/A5 Serial Data Input/Output (SDIO). When CS is pulled low, SDIO is used for reading and writing to the SPI port. Bit 5 for Parallel Gain Control Interface (A5). 8 SCLK/A4 Serial Clock Input in SPI Mode (SCLK). Bit 4 for Parallel Gain Control Interface (A4). 9 GS1/CS/A3 MSB for Gain Step Size Control in Up/Down Mode (GS1). SPI Interface Select (CS). When serial mode is enabled, a logic low (0 V ≤ CS ≤ 0.8 V) enables the SPI interface. Bit 3 for Parallel Gain Control Interface (A3). 10 GS0/FA/A2 LSB for Gain Step Size Control in Up/Down Mode (GS0). Fast Attack (FA). In serial mode, a logic high (1.4 V ≤ FA ≤ 3.3 V) attenuates according to the FA setting in the SPI word. Bit 2 for Parallel Gain Control Interface (A2). 11 UPDN_CLK/A1 Clock Interface for Up/Down Function (UPDN_CLK). Bit 1 for Parallel Gain Control Interface (A1). 12 UPDN_DAT/A0 Data Pin for Up/Down Function (UPDN_DAT). Bit 0 for Parallel Gain Control Interface (A0). 13 LATCH A logic low (0 V ≤ LATCH ≤ 0.8 V) allows gain changes. A logic high (1.4 V ≤ LATCH ≤ 3.3 V) disallows gain changes. 14, 16 VOUT+ Positive Output. 15, 17 VOUT− Negative Output. 18, 21, VPOS Positive Power Supply. 22, 23, 24 19 PWUP Power-Up Pin. A logic high (1.4 V ≤ PWUP ≤ 3.3 V) enables the part. 20 PM Performance Mode. A logic low (0 V ≤ PM ≤ 0.8 V) enables high performance mode. A logic high (2.8 V ≤ PM ≤ 3.3 V) enables low power mode. Rev. C | Page 6 of 26 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS CHARACTERIZATION AND TEST CIRCUITS THEORY OF OPERATION DIGITAL INTERFACE OVERVIEW PARALLEL DIGITAL INTERFACE SERIAL PERIPHERAL INTERFACE (SPI) Fast Attack UP/DOWN INTERFACE Truth Table LOGIC TIMING CIRCUIT DESCRIPTION BASIC STRUCTURE INPUT SYSTEM OUTPUT AMPLIFIER GAIN CONTROL APPLICATIONS INFORMATION BASIC CONNECTIONS ADC DRIVING LAYOUT CONSIDERATIONS EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS Configuration Options for the Main Section Configuration Options for the USB Section OUTLINE DIMENSIONS ORDERING GUIDE