Datasheet ADRF6510 (Analog Devices)

30 MHz Dual Programmable Filters and Variable Gain Amplifiers Data Sheet ADRF6510 FEATURES FUNCTIONAL BLOCK DIAGRAM Matched pair of programmable filters and VGAs ENBL INP1 INM1 VPS COM GNSW OFS1 VPS Continuous gain control range: −5 dB to +45 dB 6-pole filter VPSD OPP1 1 MHz to 30 MHz in 1 MHz steps, 0.5 dB corner frequency COMD OPM1 SPI programmable LE COM 6 dB front-end gain step IMD3: >55 dBc for 1.5 V p-p composite output CLK GAIN SPI ADRF6510 HD2, HD3: >60 dBc for 1.5 V p-p output DATA VOCM Differential input and output SDO COM Adjustable output common-mode voltage COM OPM2 Optional dc output offset correction Power-down feature VPS OPP2 Single 5 V supply operation
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APPLICATIONS COM INP2 INM2 VPS COM OFDS OFS2 VPS
09002- Figure 1.
Baseband I/Q receivers Diversity receivers ADC drivers GENERAL DESCRIPTION
The ADRF6510 is a matched pair of fully differential low noise The variable gain amplifiers that follow the filters provide 50 dB and low distortion programmable filters and variable gain ampli- of continuous gain control with a slope of 30 mV/dB. The output fiers (VGAs). Each channel is capable of rejecting large out-of- buffers provide a differential output impedance of 20 Ω that is band interferers while reliably boosting the wanted signal, thus capable of driving 1.5 V p-p into 1 kΩ loads. The output common- reducing the bandwidth and resolution requirements on the mode voltage defaults to VPS/2, but it can be programmed via the analog-to-digital converters (ADCs). The excellent matching VOCM pin. The built-in dc offset correction loop can be disabled between channels and their high spurious-free dynamic range if dc-coupled operation is desired. The high-pass corner frequency over all gain and bandwidth settings makes the ADRF6510 is defined by external capacitors on the OFS1 and OFS2 pins. ideal for quadrature-based (IQ) communication systems with The ADRF6510 operates from a 4.75 V to 5.25 V supply and dense constellations, multiple carriers, and nearby interferers. consumes a maximum supply current of 258 mA when pro- The filters provide a six-pole Butterworth response with 0.5 dB grammed to the highest bandwidth setting. When disabled, it corner frequencies programmable through the SPI port from consumes 2 mA. The ADRF6510 is fabricated in an advanced 1 MHz to 30 MHz in 1 MHz steps. The preamplifier that precedes silicon-germanium BiCMOS process and is available in a the filters offers a pin-programmable option of either 6 dB or 32-lead, exposed paddle LFCSP. Performance is specified over 12 dB of gain. The preamplifier sets a differential input imped- the −40°C to +85°C temperature range. ance of 400 Ω and has a common-mode voltage that defaults to 2.1 V but can be driven from 1.5 V to 2.5 V.
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Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT BUFFERS PROGRAMMABLE FILTERS VARIABLE GAIN AMPLIFIERS (VGAs) OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE FILTERS NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS APPLICATIONS INFORMATION BASIC CONNECTIONS ERROR VECTOR MAGNITUDE (EVM) PERFORMANCE EVM EFFECT OF FILTER BANDWIDTH ON EVM EFFECT OF OUTPUT VOLTAGE LEVELS ON EVM EFFECT OF COFS ON EVM ANTI-ALIASING FILTER EVALUATION BOARD EVALUATION BOARD CONTROL SOFTWARE SCHEMATICS AND ARTWORK EVALUATION BOARD CONFIGURATION OPTIONS USB Section Configuration Options OUTLINE DIMENSIONS ORDERING GUIDE