Datasheet ADL5330 (Analog Devices) - 4

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ADL5330 Data Sheet Parameter Conditions Min Typ Max Unit
Input Return Loss2 1 V < VGAIN < 1.4 V −18 dB Output Return Loss2 −18 dB 2200 MHz Gain Control Span ±3 dB gain law conformance 46 dB Maximum Gain VGAIN = 1.4 V 16 dB Minimum Gain VGAIN = 0.6 V −30 dB Gain Flatness vs. Frequency ±30 MHz around center frequency, 0.23 dB VGAIN = 1.0 V (differential output) Gain Control Slope 16.7 mV/dB Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 1.06 V Input Compression Point VGAIN = 1.2 V 0.9 dBm Input Compression Point VGAIN = 1.4 V −2.0 dBm Output Third-Order Intercept (OIP3) VGAIN = 1.4 V 21.2 dBm Output Noise Floor1 20 MHz carrier offset, VGAIN = 1.4 V −147 dBm/Hz Noise Figure VGAIN = 1.4 V 12.5 dB Input Return Loss2 1 V < VGAIN < 1.4 V −11.7 dB Output Return Loss2 −9.5 dB 2700 MHz Gain Control Span ±3 dB gain law conformance 42 dB Maximum Gain VGAIN = 1.4 V 10 dB Minimum Gain VGAIN = 0.7 V −32 dB Gain Flatness vs. Frequency ±30 MHz around center frequency, 0.3 dB VGAIN = 1.0 V (differential output) Gain Control Slope 16 mV/dB Gain Control Intercept Gain = 0 dB, gain = slope (VGAIN − intercept) 1.15 V Input Compression Point VGAIN = 1.2 V 1.2 dBm Input Compression Point VGAIN = 1.4 V −0.9 dBm Output Third-Order Intercept (OIP3) VGAIN = 1.4 V 17 dBm Output Noise Floor1 20 MHz carrier offset, VGAIN = 1.4 V −152 dBm/Hz Noise Figure VGAIN = 1.4 V 14.7 dB Input Return Loss2 1 V < VGAIN < 1.4 V −9.7 dB Output Return Loss2 −5 dB GAIN CONTROL INPUT GAIN pin Gain Control Voltage Range3 0 1.4 V Incremental Input Resistance GAIN pin to COM1 pin 1 MΩ Response Time Full scale: to within 1 dB of final gain 380 ns 3 dB gain step, POUT to within 1 dB of final gain 20 ns POWER SUPPLIES Pin VPS1, Pin VPS2, Pin COM1, Pin COM2, Pin ENBL Voltage 4.75 5 5.25 V Current, Nominal Active VGN = 0 V 100 mA VGN = 1.4 V 215 mA Current, Disabled ENBL = LO 250 μA 1 Noise floor varies slightly with output power level. See Figure 9 to Figure 13. 2 See Figure 27 and Figure 29 for differential input and output impedances. 3 Minimum gain voltage varies with frequency. See Figure 3 to Figure 7. Rev. B | Page 4 of 24 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION BASIC CONNECTIONS RF INPUT/OUTPUT INTERFACE GAIN CONTROL INPUT AUTOMATIC GAIN CONTROL INTERFACING TO AN IQ MODULATOR WCDMA TRANSMIT APPLICATION CDMA2000 TRANSMIT APPLICATION SOLDERING INFORMATION EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE