Datasheet ADL5331 (Analog Devices) - 8

FabricanteAnalog Devices
Descripción1 MHz to 1.2 GHz VGA with 30 dB Gain Control Range
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ADL5331. Data Sheet. THEORY OF OPERATION. TRANSIMPEDANCE. AMPLIFIER. INHI. OPHI. INLO. OPLO. Gm STAGE. GAIN. CONTROL

ADL5331 Data Sheet THEORY OF OPERATION TRANSIMPEDANCE AMPLIFIER INHI OPHI INLO OPLO Gm STAGE GAIN CONTROL

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ADL5331 Data Sheet THEORY OF OPERATION
The ADL5331 is a high performance, voltage-controlled Linear-in-dB gain control is accomplished by the application of variable gain amplifier/attenuator for use in applications a voltage in the range of 0 V dc to 1.4 V dc to the gain control with frequencies up to 1.2 GHz. This device is intended to pin, with maximum gain occurring at the highest voltage. serve as an output variable gain amplifier (OVGA) for applica- The output of the ladder attenuator is passed into a fixed-gain tions where a reasonably constant input level is available and transimpedance amplifier (TZA) to provide gain and to buffer the output level adjusts over a wide range. One aspect of an the ladder terminating impedance from load variations. The OVGA is that the output metrics, OIP3 and OP1dB, decrease TZA uses feedback to improve linearity and to provide controlled with decreasing gain. 50 Ω differential output impedance. The quiescent current of The signal path is fully differential throughout the device to the output amplifier is adaptive; it is controlled by an output provide the usual benefits of differential signaling, including level detector, which biases the output stage for signal levels reduced radiation, reduced parasitic feedthrough, and reduced above a threshold. susceptibility to common-mode interference with other circuits. The outputs of the ADL5331 require external dc bias to the Figure 14 provides a simplified schematic of the ADL5331. positive supply voltage. This bias is typically supplied through external inductors. The outputs are best taken differentially to avoid any common-mode noise that is present, but, if necessary,
TRANSIMPEDANCE AMPLIFIER
can be taken single-ended from either output.
INHI OPHI
The output impedance is 20 Ω differential and can drive a range
INLO OPLO
of impedances from <20 Ω to >75 Ω. Back series terminations
Gm STAGE
can be used to pad the output impedance to a desired level. If only a single output is used, it is still necessary to provide a
GAIN
16 bias to the unused output pin and it is advisable to arrange a 0
CONTROL
3- 59 reasonably equivalent ac load on the unused output. Differential 07 Figure 14. Simplified Schematic output can be taken via a 1:1 balun into a 50 Ω environment. In virtually all cases, it is necessary to use dc blocking in the output A controlled input impedance of 50 Ω is achieved through signal path. a combination of passive and active (feedback-derived) termination techniques in an input Gm stage. At high gain settings, the noise floor is set by the input stage, in which case the noise figure (NF) of the device is essentially Note that the inputs of the Gm stage are internally biased to independent of the gain setting. Below a certain gain setting, a dc level and dc blocking capacitors are generally needed on however, the input stage noise that reaches the output of the the inputs to avoid upsetting the operation of the device. attenuator falls below the input-equivalent noise of the output The currents from the Gm stage are then injected into a stage. In such a case, the output noise is dominated by the output balanced ladder attenuator at a deliberately diffused location stage itself; therefore, the overall NF of the device gets worse along the ladder, wherein the location of the centroid of the on a dB-per-dB basis as the gain is lowered, because the gain injection region is dependent on the applied gain control is reduced below the critical value. Figure 7 through Figure 9 voltage. The steering of the current injection into the ladder provide details of this behavior. is accomplished by proprietary means to achieve linear-in-dB gain control and low distortion. Rev. A | Page 8 of 15 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION APPLICATIONS INFORMATION BASIC CONNECTIONS GAIN CONTROL INPUT CMTS TRANSMIT APPLICATION Interfacing to AD9789 INTERFACING TO AN IQ MODULATOR SOLDERING INFORMATION EVALUATION BOARD SCHEMATIC OUTLINE DIMENSIONS ORDERING GUIDE