Datasheet AD9218-EP (Analog Devices)
Fabricante | Analog Devices |
Descripción | 10-Bit, 40/65/80/105 MSPS 3 V Dual A/D Converter |
Páginas / Página | 11 / 1 — 10-Bit, 105 MSPS, 3 V, Dual ADC. Enhanced Product. AD9218-EP. FEATURES. … |
Formato / tamaño de archivo | PDF / 217 Kb |
Idioma del documento | Inglés |
10-Bit, 105 MSPS, 3 V, Dual ADC. Enhanced Product. AD9218-EP. FEATURES. GENERAL DESCRIPTION. Dual, 10-bit, 105 MSPS ADC
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10-Bit, 105 MSPS, 3 V, Dual ADC Enhanced Product AD9218-EP FEATURES GENERAL DESCRIPTION Dual, 10-bit, 105 MSPS ADC
The AD9218-EP is a dual, 10-bit, monolithic sampling analog-
Low power: 275 mW at 105 MSPS per channel
to-digital converter (ADC) with on-chip track-and-hold
On-chip reference and track-and-hold
circuits. The product is low cost, low power, and is small and
300 MHz analog bandwidth for each channel
easy to use. The AD9218-EP operates at a 105 MSPS conversion
SNR = 54 dB at 51 MHz, encode = 105 MSPS
rate with dynamic performance over its full operating range.
1 V p-p analog input range for each channel
Each channel can be operated independently.
3.0 V single-supply operation (2.7 V to 3.6 V)
The ADC requires only a single 3.0 V (2.7 V to 3.6 V) power
Power-down mode for single-channel operation
supply and a clock for full operation. No external reference or
Twos complement or offset binary output mode
driver components are required for many applications. The
Output data alignment mode
digital outputs are transistor-to-transistor logic (TTL)/
–75 dBc crosstalk between channels
complementary metal-oxide semiconductor (CMOS)
ENHANCED PRODUCT FEATURES
compatible, and a separate output power supply pin supports
Supports defense and aerospace applications
interfacing with 3.3 V or 2.5 V logic.
(AQEC standard)
The clock input is TTL/CMOS compatible and the 10-bit digital
Extended industrial temperature range: −55°C to +105°C
outputs can be operated from a 3.0 V (2.5 V to 3.6 V) supply.
Controlled manufacturing baseline
User-selectable options offer a combination of power-down
1 assembly/test site
modes, digital data formats, and digital data timing schemes.
1 fabrication site
In power-down mode, the digital outputs are driven to a high
Product change notification
impedance state.
Qualification data available on request
The AD9218-EP is fabricated on an advanced CMOS process
APPLICATIONS
and is available in a 48-lead, 7 mm × 7 mm, low profile quad
Radar
flat package (LQFP), and is specified over the extended
Avionics
industrial temperature range of −55°C to +105°C.
Unmanned systems
Additional application and technical information can be found
Military communications
in the AD9218 data sheet.
Missiles and munitions FUNCTIONAL BLOCK DIAGRAM ENC TIMING AD9218-EP A AINA OUTPUT T/H ADC / / D9A TO D0A REGISTER A 10 10 INA S1 REFINA REFOUT REF S2 REFINB DFS/GAIN AINB OUTPUT T/H ADC / / D9B TO D0B A REGISTER 10 10 INB ENCB TIMING
001
VD GND VDD
17309- Figure 1.
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Document Outline FEATURES ENHANCED PRODUCT FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS DIGITAL SPECIFICATIONS AC SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS EXPLANATION OF TEST LEVELS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS OUTLINE DIMENSIONS ORDERING GUIDE