link to page 6 ADW12001DIGITAL SPECIFICATIONS AVDD = 3 V, DRVDD = 2.5 V, maximum sample rate, CLK_A = CLK_B; AIN = −0.5 dBFS differential input, 1.0 V internal reference, TMIN to TMAX, DCS enabled, unless otherwise noted. Table 3.25°C/115°CParameterTempMinTypMaxUnit LOGIC INPUTS High Level Input Voltage Full 2.0 V Low Level Input Voltage Full 0.8 V High Level Input Current Full −10 +10 μA Low Level Input Current Full −10 +10 μA Input Capacitance Full 2 pF LOGIC OUTPUTS1 High Level Output Voltage Full DRVDD − 0.05 V Low Level Output Voltage Full 0.05 V 1 Output voltage levels measured with capacitive load only on each output. Rev. 0 | Page 6 of 24 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TERMINOLOGY TYPICAL PERFORMANCE CHARACTERISTICS EQUIVALENT CIRCUITS THEORY OF OPERATION ANALOG INPUT Differential Input Configurations Single-Ended Input Configuration CLOCK INPUT AND CONSIDERATIONS POWER DISSIPATION AND STANDBY MODE DIGITAL OUTPUTS TIMING DATA FORMAT VOLTAGE REFERENCE Internal Reference Connection External Reference Operation THERMAL CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE