Datasheet AD9276 (Analog Devices) - 3

AD9276 GENERAL DESCRIPTION
The AD9276 is designed for low cost, low power, small size, The AD9276 requires a LVPECL-/CMOS-/LVDS-compatible and ease of use. It contains eight channels of a variable gain sample rate clock for full performance operation. No external amplifier (VGA) with a low noise preamplifier (LNA); an anti- reference or driver components are required for many applications. aliasing filter (AAF); a 12-bit, 10 MSPS to 80 MSPS analog-to- The ADC automatically multiplies the sample rate clock for digital converter (ADC); and an I/Q demodulator with the appropriate LVDS serial data rate. A data clock (DCO±) for programmable phase rotation. capturing data on the output and a frame clock (FCO±) trigger Each channel features a variable gain range of 42 dB, a fully for signaling a new output byte are provided. differential signal path, an active input preamplifier termination, Powering down individual channels is supported to increase a maximum gain of up to 52 dB, and an ADC with a conversion battery life for portable applications. A standby mode option rate of up to 80 MSPS. The channel is optimized for dynamic allows quick power-up for power cycling. In CW Doppler opera- performance and low power in applications where a small tion, the VGA, AAF, and ADC are powered down. The power of package size is critical. the TGC path scales with selectable ADC speed power modes. The LNA has a single-ended-to-differential gain that is selectable The ADC contains several features designed to maximize flexibility through the SPI. The LNA input noise is typically 0.75 nV/√Hz and minimize system cost, such as a programmable clock, data at a gain of 21.3 dB, and the combined input-referred noise of alignment, and programmable digital test pattern generation. The the entire channel is 0.85 nV/√Hz at maximum gain. Assuming digital test patterns include built-in fixed patterns, built-in pseudo- a 15 MHz noise bandwidth (NBW) and a 21.3 dB LNA gain, the random patterns, and custom user-defined test patterns entered input SNR is roughly 92 dB. In CW Doppler mode, each LNA via the serial port interface. output drives an I/Q demodulator. Each demodulator has inde- pendently programmable phase rotation through the SPI with Fabricated in an advanced CMOS process, the AD9276 is 16 phase settings. available in a 16 mm × 16 mm, RoHS compliant, 100-lead TQFP. It is specified over the industrial temperature range of −40°C to +85°C. Rev. 0 | Page 3 of 48 Document Outline FEATURES APPLICATIONS PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE EQUIVALENT CIRCUITS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information TGC OPERATION Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode DIGITAL OUTPUTS AND TIMING SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS APPLICATIONS INFORMATION POWER AND GROUND RECOMMENDATIONS EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE