Datasheet AD9277 (Analog Devices) - 6

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AD9277 Parameter1 Test Conditions/Comments Min Typ Max Unit
Noise Figure RS = 50 Ω, RFB = ∞ LNA gain = 15.6 dB 5.7 dB LNA gain = 17.9 dB 5.3 dB LNA gain = 21.3 dB 4.8 dB Input-Referred Dynamic Range RS = 0 Ω, RFB = ∞ LNA gain = 15.6 dB 164 dBFS/√Hz LNA gain = 17.9 dB 162 dBFS/√Hz LNA gain = 21.3 dB 160 dBFS/√Hz Output-Referred SNR −3 dBFS input, fRF = 2.5 MHz, f4LO = 10 MHz, 155 dBc/√Hz 1 kHz offset Two-Tone Intermodulation (IMD3) fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, −58 dB f4LO = 20 MHz, ARF1 = 0 dB, ARF2 = −20 dB, IMD3 relative to ARF2 Quadrature Phase Error I to Q, all phases, 1 σ 0.15 Degrees I/Q Amplitude Imbalance I to Q, all phases, 1 σ 0.015 dB Channel-to-Channel Matching Phase I to I, Q to Q, 1 σ 0.5 Degrees Amplitude I to I, Q to Q, 1 σ 0.25 dB POWER SUPPLY AVDD1 1.7 1.8 1.9 V AVDD2 2.7 3.0 3.6 V DRVDD 1.7 1.8 1.9 V IAVDD1 TGC mode 265 mA CW Doppler mode 15 mA IAVDD2 TGC mode, no signal 365 mA CW Doppler mode per channel enabled, 30 mA no signal IDRVDD 51 mA Total Power Dissipation TGC mode, no signal 1660 1930 mW (Including Output Drivers) CW Doppler mode with eight channels 750 mW enabled, no signal Power-Down Dissipation 5 mW Standby Power Dissipation 200 mW Power Supply Rejection Ratio 1.6 mV/V (PSRR) ADC RESOLUTION 14 Bits ADC REFERENCE Output Voltage Error VREF = 1 V ±20 mV Load Regulation at 1.0 mA VREF = 1 V 2 mV Input Resistance 6 kΩ 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 The overrange condition is specified as being 6 dB more than the full-scale input range. Rev. 0 | Page 6 of 48 Document Outline FEATURES APPLICATIONS PRODUCT HIGHLIGHTS FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC TIMING DIAGRAMS ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE EQUIVALENT CIRCUITS THEORY OF OPERATION ULTRASOUND CHANNEL OVERVIEW Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise INPUT OVERDRIVE Input Overload Protection CW DOPPLER OPERATION Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information TGC OPERATION Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode DIGITAL OUTPUTS AND TIMING SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS APPLICATIONS INFORMATION POWER AND GROUND RECOMMENDATIONS EXPOSED PADDLE THERMAL HEAT SLUG RECOMMENDATIONS OUTLINE DIMENSIONS ORDERING GUIDE