Datasheet AD9650-EP (Analog Devices)

Dual 16-Bit, 105 MSPS, 1.8 V Analog-to-Digital Converter Data Sheet AD9650-EP FEATURES FUNCTIONAL BLOCK DIAGRAM Dual 16-bit ADC in enhanced package for extended SDIO/ SCLK/ AVDD CSB DRVDD DCS DFS temperature range of −55°C to +85°C 1.8 V analog supply operation SPI AD9650-EP LVDS output SNR: 80.5 dBFS at 30 MHz input and 105 MSPS data rate PROGRAMMING DATA OR+ SFDR: 93 dBc at 30 MHz input and 105 MSPS data rate VIN+A D15+ (MSB) CMOS/LVDS 16 Low power: 328 mW per channel at 105 MSPS ADC OUTPUT BUFFER TO VIN–A D0+ (LSB) Integer 1-to-8 input clock divider IF sampling frequencies up to 300 MHz DIVIDE 1 CLK+ VREF Analog input range of 2.7 V p-p TO 8 CLK– SENSE Optional on-chip dither DUTY CYCLE DCO DCO+ Integrated ADC sample-and-hold inputs REF STABILIZER GENERATION DCO– VCM SELECT Differential analog inputs with 500 MHz bandwidth RBIAS ADC clock duty cycle stabilizer (DCS) OR– D15– (MSB) VIN–B CMOS/LVDS 16 APPLICATIONS ADC TO OUTPUT BUFFER VIN+B D0– (LSB) Radar MULTICHIP Electronic warfare (EW) systems SYNC Joint tactical radio system (JTRS) and other COMSEC AGND SYNC PDWN OEB Industrial instrumentation
001
X-ray, MRI, and ultrasound equipment NOTES 1. PIN NAMES ARE FOR THE LVDS PIN CONFIGURATION ONLY.
11312-
High speed pulse acquisition
Figure 1.
Chemical and spectrum analysis General-purpose software radios GENERAL DESCRIPTION
The AD9650-EP is a dual 16-bit, 105 MSPS analog-to-digital Additional application and technical information can be found converter (ADC) designed for digitizing high frequency, wide in the AD9650 data sheet. dynamic range signals with input frequencies of up to 300 MHz.
PRODUCT HIGHLIGHTS
The dual ADC core features a multistage differential pipelined 1. On-chip dither option for improved SFDR performance architecture with integrated output error correction logic. Each with low power analog input. ADC features wide bandwidth, differential sample-and-hold analog 2. Proprietary differential input that maintains excel ent SNR input amplifiers, and a shared integrated voltage reference, which performance for input frequencies up to 300 MHz. eases design considerations. A duty cycle stabilizer (DCS) is pro- 3. Operation from a single 1.8 V supply with a separate digital vided to compensate for variations in the ADC clock duty cycle, output driver supply that accommodates 1.8 V CMOS or allowing the converters to maintain excellent performance. LVDS outputs. The ADC output data can be routed directly to the two external 4. Standard serial port interface (SPI) that supports various 16-bit output ports or multiplexed on a single 16-bit bus. These product features and functions such as data formatting outputs can be set to either 1.8 V CMOS or LVDS. (offset binary, twos complement, or Gray coding), enabling Flexible power-down options al ow significant power savings, the clock DCS, power-down, and test modes. when desired. Programming for setup and control is accomplished 5. 12 mm × 12 mm, 80-lead TQFP with an exposed pad using a 3-wire, SPI-compatible serial interface. (7.5 mm × 7.5 mm). The AD9650-EP is available in an 80-lead TQFP and is specified over the extended temperature range of −55°C to +85°C.
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Document Outline Features Applications Functional Block Diagram General Description Product Highlights Table of Contents Revision History Specifications ADC DC Specifications ADC AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Outline Dimensions Ordering Guide