Datasheet AD9278 (Analog Devices) - 2
| Fabricante | Analog Devices |
| Descripción | Octal LNA/VGA/AAF/ADC and CW I/Q Demodulator |
| Páginas / Página | 44 / 2 — AD9278. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY /12—Rev. 0 to … |
| Revisión | A |
| Formato / tamaño de archivo | PDF / 885 Kb |
| Idioma del documento | Inglés |
AD9278. Data Sheet. TABLE OF CONTENTS. REVISION HISTORY /12—Rev. 0 to Rev. A. 10/10—Revision 0: Initial Version
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AD9278 Data Sheet TABLE OF CONTENTS
Features .. 1 Equivalent Circuits ... 17 General Description ... 1 Ultrasound Theory of Operation ... 19 Functional Block Diagram .. 1 Channel Overview .. 20 Revision History ... 2 TGC Operation ... 20 Specifications ... 3 CW Doppler Operation ... 33 AC Specifications .. 3 Serial Port Interface (SPI) .. 37 Digital Specifications ... 6 Hardware Interface ... 37 Switching Specifications .. 7 Memory Map .. 39 ADC Timing Diagrams ... 8 Reading the Memory Map Table .. 39 Absolute Maximum Ratings .. 9 Reserved Locations .. 39 Thermal Impedance ... 9 Default Values ... 39 ESD Caution .. 9 Logic Levels ... 39 Pin Configuration and Function Descriptions ... 10 Outline Dimensions ... 43 Typical Performance Characteristics ... 13 Ordering Guide .. 43 TGC Mode ... 13 CW Doppler Mode ... 16
REVISION HISTORY /12—Rev. 0 to Rev. A
Changes to SNR in Features Section .. 1 Added Mode IV to Table 1 and Table 1 Conditions .. 3 Added Mode IV Clock Rate Parameters and Changed tEH and tEL from 6.25 ns to 4.8 ns; Table 3 .. ... ... ... .. .. .. .. ... ... ... ... ... 7 Changes to Active Impedance Matching Section ... 23 Added Table 9 .. 24 Changes to Figure 56 and Figure 57 ... 28 Changes to Digital Outputs and Timing Section ... 30 Changes to 0x01 Bits[7:0] Description, Changes to 0x02 Bits[5:4] Description and Default Value; Table 19 ... 40 Updated Outline Dimensions ... 43
10/10—Revision 0: Initial Version
Rev. A | Page 2 of 44 Document Outline Features General Description Functional Block Diagram Revision History Specifications AC Specifications Digital Specifications Switching Specifications ADC Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics TGC Mode CW Doppler Mode Equivalent Circuits Ultrasound Theory of Operation Channel Overview TGC Operation Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise Input Overdrive Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Recommendations Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference CW Doppler Operation Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Outline Dimensions Ordering Guide
AD9278 Data Sheet TABLE OF CONTENTS
Features .. 1 Equivalent Circuits ... 17 General Description ... 1 Ultrasound Theory of Operation ... 19 Functional Block Diagram .. 1 Channel Overview .. 20 Revision History ... 2 TGC Operation ... 20 Specifications ... 3 CW Doppler Operation ... 33 AC Specifications .. 3 Serial Port Interface (SPI) .. 37 Digital Specifications ... 6 Hardware Interface ... 37 Switching Specifications .. 7 Memory Map .. 39 ADC Timing Diagrams ... 8 Reading the Memory Map Table .. 39 Absolute Maximum Ratings .. 9 Reserved Locations .. 39 Thermal Impedance ... 9 Default Values ... 39 ESD Caution .. 9 Logic Levels ... 39 Pin Configuration and Function Descriptions ... 10 Outline Dimensions ... 43 Typical Performance Characteristics ... 13 Ordering Guide .. 43 TGC Mode ... 13 CW Doppler Mode ... 16
REVISION HISTORY /12—Rev. 0 to Rev. A
Changes to SNR in Features Section .. 1 Added Mode IV to Table 1 and Table 1 Conditions .. 3 Added Mode IV Clock Rate Parameters and Changed tEH and tEL from 6.25 ns to 4.8 ns; Table 3 .. ... ... ... .. .. .. .. ... ... ... ... ... 7 Changes to Active Impedance Matching Section ... 23 Added Table 9 .. 24 Changes to Figure 56 and Figure 57 ... 28 Changes to Digital Outputs and Timing Section ... 30 Changes to 0x01 Bits[7:0] Description, Changes to 0x02 Bits[5:4] Description and Default Value; Table 19 ... 40 Updated Outline Dimensions ... 43
10/10—Revision 0: Initial Version
Rev. A | Page 2 of 44 Document Outline Features General Description Functional Block Diagram Revision History Specifications AC Specifications Digital Specifications Switching Specifications ADC Timing Diagrams Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics TGC Mode CW Doppler Mode Equivalent Circuits Ultrasound Theory of Operation Channel Overview TGC Operation Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise Input Overdrive Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Recommendations Digital Outputs and Timing SDIO Pin SCLK Pin CSB Pin RBIAS Pin Voltage Reference CW Doppler Operation Quadrature Generation I/Q Demodulator and Phase Shifter Dynamic Range and Noise Phase Compensation and Analog Beamforming CW Application Information Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Outline Dimensions Ordering Guide