Datasheet AD9284 (Analog Devices) - 10

AD9284 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS
AVDD = 1.8 V, DRVDD = 1.8 V, sample rate = 250 MSPS, DCS enabled, 1.2 V p-p differential input, VIN = −1.0 dBFS, 64k sample, TA = 25°C, unless otherwise noted.
0 0 250MSPS 250MSPS 4.3MHz @ –1dBFS 96.6MHz @ –1dBFS SNR = 48.3dB (49.3dBFS) SNR = 48.3dB (49.3dBFS) –20 ENOB = 7.7 –20 ENOB = 7.7 SFDR = 70.3dBc SFDR = 70.0dBc ) ) S –40 S –40 BF BF d d SECOND HARMONIC ( SECOND HARMONIC –60 –60 UDE ( UDE THIRD HARMONIC IT IT L THIRD HARMONIC L P P –80 AM –80 AM –100 –100 –120 –120 0 25 50 75 100 125
107
0 25 50 75 100 125
110
FREQUENCY (MHz) FREQUENCY (MHz)
09085- 09085- Figure 4. Single-Tone FFT with fIN = 4.3 MHz Figure 7. Single-Tone FFT with fIN = 96.6 MHz
0 0 250MSPS 250MSPS 330.3MHz @ –1dBFS 29.2MHz @ –7dBFS SNR = 48.2dB (49.2dBFS) 32.2MHz @ –7dBFS –20 –20 ENOB = 7.6 SFDR = 69.6dBc (76.6dBFS) SFDR = 60.9dBc ) S –40 S) –40 F BF B d d ( E THIRD HARMONIC –60 –60 SECOND HARMONIC UDE ( UD IT L IT P L P –80 AM –80 AM –100 –100 –120 0 25 50 75 100 125
111
–120 FREQUENCY (MHz) 0 25 50 75 100 125
09085- 108
FREQUENCY (MHz)
09085- Figure 5. Single-Tone FFT with fIN = 220.3 MHz Figure 8. Two-Tone FFT with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz
80 80 IMD3 (dBFS) 70 70 SFDR (dBFS) 60 60 SFDR (dBFS) SNR (dBFS) B) 50 B) 50 d d ( NR ( REFERENCE LINE D3 40 40 /S SFDR (dBc) /IM IMD3 (dBc) DR F DR 30 S 30 SF SFDR (dBc) 20 SNR (dBc) 20 10 10 0 0 –45 –40 –35 –30 –25 –20 –15 –10 –5 0
109
–45 –40 –35 –30 –25 –20 –15 –10 –5 0
112 85- 85-
AIN POWER (dBFS) AIN POWER (dBFS)
090 090 Figure 6. SFDR/SNR vs. Input Amplitude (AIN) with fIN = 2.2 MHz Figure 9. Two-Tone SFDR/IMD3 vs. Input Amplitude (AIN) with fIN1 = 29.1 MHz and fIN2 = 32.1 MHz Rev. A | Page 10 of 24 Document Outline Features Applications General Description Product Highlights Functional Block Diagram Revision History Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications SPI Timing Specifications Timing Diagram Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Differential Input Configurations Voltage Reference RBIAS Clock Input Considerations Clock Input Options Digital Outputs Digital Output Enable Function () Built-In Self-Test (BIST) and Output Test Built-In Self-Test (BIST) Output Test Modes Serial Port Interface (SPI) Configuration Using the SPI Hardware Interface Configuration Without the SPI SPI Accessible Features Memory Map Reading the Memory Map Register Table Open Locations Default Values Logic Levels Transfer Register Map Channel-Specific Registers Memory Map Register Table Memory Map Register Descriptions Voltage Reference (Register 0x18) Bits[7:5]—Reserved Bits[4:0]—Voltage Reference Applications Information Design Guidelines Power and Ground Recommendations Exposed Paddle Thermal Heat Sink Recommendations VCM RBIAS Reference Decoupling SPI Port Outline Dimensions Ordering Guide