Datasheet LTM9011-14, LTM9010-14, LTM9009-14 (Analog Devices)

LTM9011-14/ LTM9010-14/LTM9009-14 14-Bit, 125Msps/105Msps/ 80Msps Low Power Octal ADCs FEATURES DESCRIPTION n
8-Channel Simultaneous Sampling ADC
The LTM®9011-14/LTM9010-14/LTM9009-14 are 8-chan- n
73.1dB SNR
nel, simultaneous sampling 14-bit A/D converters designed n
88dB SFDR
for digitizing high frequency, wide dynamic range signals. n Low Power: 140mW/113mW/94mW per Channel AC performance includes 73.1dB SNR and 88dB spurious n Single 1.8V Supply free dynamic range (SFDR). Low power consumption per n Serial LVDS Outputs: 1 or 2 Bits per Channel channel reduces heat in high channel count applications. n Selectable Input Ranges: 1V Integrated bypass capacitance and flow-through pinout P-P to 2VP-P n 800MHz Full Power Bandwidth S/H reduces overall board space requirements. n Shutdown and Nap Modes DC specs include ±1LSB INL (typ), ±0.3LSB DNL (typ) n Serial SPI Port for Configuration and no missing codes over temperature. The transition n Internal Bypass Capacitance, No External noise is a low 1.2LSBRMS. Components n The digital outputs are serial LVDS to minimize the num- 140-Pin (11.25mm × 9mm) BGA Package ber of data lines. Each channel outputs two bits at a time APPLICATIONS (2-lane mode). At lower sampling rates there is a one bit per channel option (1-lane mode). n Communications The ENC+ and ENC– inputs may be driven differentially n Cellular Base Stations or single-ended with a sine wave, PECL, LVDS, TTL, or n Software Defined Radios CMOS inputs. An internal clock duty cycle stabilizer al- n Portable Medical Imaging lows high performance at full speed for a wide range of n Multichannel Data Acquisition clock duty cycles. n Nondestructive Testing All registered trademarks and trademarks are the property of their respective owners. TYPICAL APPLICATION 1.8V 1.8V
LTM9011-14, 125Msps,
VDD OVDD
2-Tone FFT, fIN = 70MHz and 75MHz
CHANNEL 1 14-BIT OUT1A 0 ANALOG S/H ADC CORE INPUT OUT1B –10 –20 CHANNEL 2 14-BIT OUT2A –30 ANALOG S/H ADC CORE INPUT OUT2B –40 DATA SERIALIZED –50 SERIALIZER LVDS –60 • • • • • • • • • • • • OUTPUTS –70 CHANNEL 8 OUT8A 14-BIT ANALOG S/H ADC CORE AMPLITUDE (dBFS) –80 OUT8B INPUT –90 DATA –100 CLOCK ENCODE PLL OUT –110 INPUT –120 FRAME 0 10 20 30 40 50 60 FREQUENCY (MHz) 9009101114 TA01b GND GND 9009101114 TA01 Rev D Document Feedback For more information www.analog.com 1 Document Outline Features Applications Description Typical Application Absolute Maximum Ratings Pin Configuration Order Information Converter Characteristics Analog Input Dynamic Accuracy Internal Reference Characteristics Digital Inputs And Outputs Power Requirements Timing Characteristics Timing Diagrams Typical Performance Characteristics Pin Functions Pin Configuration Table Functional Block Diagram Applications Information Typical Applications Package Description Revision History Typical Application Related Parts