link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 AD8284Data SheetParameter1Test Conditions/CommentsMinTypMaxUnit Power-Down Dissipation TA = −25°C to +105°C 2.5 4.0 mW TA = −40°C to +25°C 2.5 8.0 mW Power Supply Rejection Ratio (PSRR)2 Relative to input 1.6 mV/V ADC Resolution2 12 Bits Maximum Sample Rate 60 MSPS Signal-to-Noise Ratio (SNR) fIN = 1 MHz 67 dB Signal-to-Noise-and-Distortion Ratio 66 dB (SINAD) 2 SNRFS2 68 dB Differential Nonlinearity (DNL) Guaranteed no missing codes 1 LSB Integral Nonlinearity (INL) fS = 60 MSPS 4 10 LSB Effective Number of Bits (ENOB)2 10.67 LSB ADC Output Characteristics2 Maximum Capacitor Load Per bit 20 pF IDVDD33 Peak Current with Capacitor Peak current per bit when driving a 20 pF load; can be 40 mA Load2 programmed via the SPI port, if required ADC REFERENCE Output Voltage Error VREF = 1.000 V ±20 mV Load Regulation At 1.0 mA, VREF = 1.000 V 2 mV Current Output −1 +1 mA Input Resistance 6 kΩ FULL CHANNEL CHARACTERISTICS LNA, PGA, AAF, and ADC SNRFS fIN = 1 MHz, −10 dBFS output Gain = 17 dB, fS = 60 MSPS 60 64 dBFS Gain = 23 dB, fS = 60 MSPS 60 64 dBFS Gain = 29 dB, fS = 60 MSPS 60 64 dBFS Gain = 35 dB, fS = 60 MSPS 60 64 dBFS SINAD2 fIN = 1 MHz Gain = 17 dB 62 dB Gain = 23 dB 63 dB Gain = 29 dB 64 dB Gain = 35 dB 63 dB Spurious-Free Dynamic Range (SFDR) fIN = 1 MHz, −10 dBFS output Gain = 17 dB, fS = 60 MSPS 62 68 dBc Gain = 23 dB, fS = 60 MSPS 62 68 dBc Gain = 29 dB, fS = 60 MSPS 62 68 dBc Gain = 35 dB, fS = 60 MSPS 62 71 dBc Harmonic Distortion2 fIN = 1 MHz at −10 dBFS output Second Harmonic Gain = 17 dB −70 dBc Gain = 35 dB −70 dBc Third Harmonic Gain = 17 dB −66 dBc Gain = 35 dB −75 dBc IM3 Distortion fIN1 = 1 MHz, fIN2 = 1.1 MHz, −1 dBFS, gain = 35 dB −69 dBc Gain Response Time 600 ns Overdrive Recovery Time 200 ns 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and testing methodology. 2 Guaranteed by design only. Rev. D | Page 4 of 28 Document Outline Features Applications Functional Block Diagram General Description Table of Contents Revision History Specifications AC Specifications Digital Specifications Switching Specifications Timing and Switching Diagram Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Theory of Operation Radar Receive Path AFE Channel Overview Multiplexer Low Noise Amplifier Recommendation Antialiasing Filter Saturation Flag ADC AUX Channel Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations SDI and SDO Pins SCLK Pin CS Pin RBIAS Pin Voltage Reference Power and Ground Recommendations Exposed Pad Thermal Heat Slug Recommendations Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Caution Logic Levels Reserved Locations Default Values Application Circuits Packaging and Ordering Information Outline Dimensions Ordering Guide Automotive Products