Datasheet AD9674 (Analog Devices)

Octal Ultrasound Analog Front End Data Sheet AD9674 FEATURES GENERAL DESCRIPTION 8 channels of LNA, VGA, AAF, ADC, and digital RF decimator
The AD9674 is designed for low cost, low power, small size, and
Low power: 150 mW per channel, TGC mode, 40 MSPS;
ease of use for medical ultrasound. It contains eight channels of a
62.5 mW per channel, CW mode; <30 mW in power-down
VGA with an LNA, a CW harmonic rejection I/Q demodulator
Time gain compensation (TGC) channel input referred noise:
with programmable phase rotation, an AAF, an ADC, a digital
0.82 nV/√Hz, maximum gain
HPF, and RF decimation by 2.
Flexible power-down modes
Each channel features a maximum gain of up to 52 dB, a fully
Fast recovery from low power standby mode: <2 μs
differential signal path, and an active input preamplifier termination.
Low noise preamplifier (LNA)
The channel is optimized for high dynamic performance and
Input referred noise voltage: 0.78 nV/√Hz, gain = 21.6 dB
low power in applications where a small package size is critical.
Programmable gain: 15.6 dB/17.9 dB/21.6 dB 0.1 dB compression: 1.00 V p-p/
The LNA has a single-ended to differential gain that is selectable
0.75 V p-p/0.45 V p-p
through the serial port interface (SPI). Assuming a 15 MHz noise
Flexible active input impedance matching
bandwidth (NBW) and a 21.6 dB LNA gain, the LNA input SNR is
Variable gain amplifier (VGA)
94 dB. In CW Doppler mode, each LNA output drives an I/Q
Attenuator range: 45 dB, linear in dB gain control
demodulator that has independently programmable phase
Postamplifier gain (PGA): 21 dB/24 dB/27 dB/30 dB
rotation with 16 phase settings.
Antialiasing filter (AAF)
Power-down of individual channels is supported to increase battery
Programmable second-order low-pass filter (LPF) from 8 MHz
life for portable applications. Standby mode al ows quick power-up
to 18 MHz or 13.5 MHz to 30 MHz and high-pass filter (HPF)
for power cycling. In CW Doppler operation, the VGA, AAF, and
Analog-to-digital converter (ADC)
ADC are powered down. The ADC contains several features
Signal-to-noise ratio (SNR): 75 dB, 14 bits up to 125 MSPS
designed to maximize flexibility and minimize system cost, such as
Configurable serial low voltage differential signaling (LVDS)
a programmable clock, data alignment, and programmable digital
Continuous wave (CW) Doppler mode harmonic rejection I/Q
test pattern generation. The digital test patterns include built in
demodulator
fixed patterns, built in pseudorandom patterns, and custom
Individual programmable phase rotation
user defined test patterns entered via the SPI.
Dynamic range per channel: >160 dBFS/√Hz Close in SNR: 156 dBc/√Hz, 1 kHz offset, −3 dBFS input Radio frequency (RF) digital HPF and decimation by 2 10 mm × 10 mm, 144-ball CSP_BGA APPLICATIONS Medical imaging/ultrasound Nondestructive Testing (NDT) Rev. A Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2016 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS ADC Timing Diagram CW Doppler Timing Diagram ABSOLUTE MAXIMUM RATINGS THERMAL IMPEDANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS TGC MODE CW DOPPLER MODE THEORY OF OPERATION TGC OPERATION Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Digital Outputs and Timing Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin General-Purpose Output Pins Chip Address Pins ANALOG TEST SIGNAL GENERATION CW DOPPLER OPERATION Quadrature Generation DIGITAL RF DECIMATOR VECTOR PROFILE RF DECIMATOR DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter DIGITAL TEST WAVEFORMS Waveform Generator Channel ID and Ramp Generator DIGITAL BLOCK POWER SAVING SCHEME SERIAL PORT INTERFACE (SPI) HARDWARE INTERFACE MEMORY MAP READING THE MEMORY MAP TABLE RESERVED LOCATIONS DEFAULT VALUES LOGIC LEVELS RECOMMENDED START-UP SEQUENCE MEMORY MAP REGISTER DESCRIPTIONS Transfer (Register 0x0FF) Profile Index and Manual TX_TRIG (Register 0x10C) OUTLINE DIMENSIONS ORDERING GUIDE