Datasheet AD9675 (Analog Devices) - 6

AD9675 Data Sheet Parameter1 Test Conditions/Comments Min Typ Max Unit
Close-In SNR −3 dBFS input, fRF = 2.5 MHz, fLO = 40 MHz, 156 dBc/√Hz 1 kHz offset, 16LO mode, one channel enabled −3 dBFS input, fRF = 2.5 MHz, fLO = 40 MHz, 161 dBc/√Hz 1 kHz offset, 16LO mode, eight channels enabled Two-Tone Intermodulation fRF1 = 5.015 MHz, fRF2 = 5.020 MHz, fLO = 80 MHz, −58 dBc Distortion (IMD3) ARF1 = −1 dBFS, ARF2 = −21 dBFS, IMD3 relative to ARF2 LO Harmonic Rejection −20 dBc Quadrature Phase Error I to Q, all phases, 1 σ 0.15 Degrees I/Q Amplitude Imbalance I to Q, all phases, 1 σ 0.015 dB Channel to Channel Matching Phase I to I, Q to Q, 1 σ 0.5 Degrees Amplitude I to I, Q to Q, 1 σ 0.25 dB POWER SUPPLY Mode I/Mode II/Mode III/Mode IV AVDD1 1.7 1.8 1.9 V AVDD2 2.85 3.0 3.6 V DVDD 1.3 1.4 1.9 V DRVDD 1.7 1.8 1.9 V IAVDD1 TGC mode, low bandwidth mode 148/187/ mA 223/291 CW Doppler mode 4 mA IAVDD2 TGC mode, no signal, low bandwidth mode 230 mA TGC mode, no signal, high bandwidth mode 239 mA CW Doppler mode 140 mA IDVDD 29/46/40/61 mA DVDD = 1.8 V 38/60/54/80 mA IDRVDD Four-lane mode, JESD204B lane rates = 121/168/ mA 1.6 Gbps/2.6 Gbps/1.6 Gbps/2.5 Gbps 122/166 Two-lane mode, JESD204B lane rates = 127/186/ mA 3.2 Gbps/5.0 Gbps/3.2 Gbps/5.0 Gbps 129/184 One-lane mode, RF decimator enabled, 73/105/not mA JESD204B lane rates = 3.2 Gbps/5.0 Gbps/ valid/not valid not valid/not valid Total Power Dissipation TGC mode, no signal, two-lane mode 1200/1415/ 1445/1680/ mW (Including Output Drivers) 1365/1615 1635/1910 TGC mode, no signal, two-lane mode, 1230/1460/ mW DVDD = 1.8 V 1410/1675 CW Doppler mode, eight channels enabled 500 mW Power-Down Dissipation 5 30 mW Standby Power Dissipation 725 mW ADC Resolution 14 Bits SNR 75 dB ADC REFERENCE Output Voltage Error VREF = 1 V ±50 mV Load Regulation at 1.0 mA VREF = 1 V 2 mV Input Resistance 7.5 kΩ 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for a complete set of definitions and information about how these tests were completed. 2 The overrange condition is specified as 6 dB more than the full-scale input range. Rev. A | Page 6 of 60 Document Outline Features Applications General Description Table of Contents Revision History Functional Block Diagram Specifications AC Specifications Digital Specifications Switching Specifications CLK±, TX_TRIG± Synchronization Timing Diagram CW Timing Diagram Absolute Maximum Ratings Thermal Impedance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics TGC Mode CW Doppler Mode Theory of Operation TGC Operation Low Noise Amplifier (LNA) Active Impedance Matching LNA Noise CLNA Connection DC Offset Correction/High-Pass Filter Variable Gain Amplifier (VGA) Gain Control VGA Noise Antialiasing Filter (AAF) AAF/VGA Test Mode ADC Clock Input Considerations Clock Duty Cycle Considerations Clock Jitter Considerations Power Dissipation and Power-Down Mode Power and Ground Connection Recommendations Advanced Power Control Digital Outputs and Timing JESD204B Transmit Top Level Description JESD204B Overview JESD204B Synchronization Details CGS Phase ILAS Phase Data Transmission Phase Link Setup Parameters Disable Lanes Converter and Lane Configuration Configure the Tail Bits and Control Bits Set Lane Identification Values Set Number of Frames per Multiframe, K Enable Scramble, SCR Set Lane Synchronization Options Check FCHK, Checksum of JESD204B Interface Parameters Set Additional Digital Output Configuration Options Reenable Lanes After Configuration Frame and Lane Alignment Monitoring and Correction Digital Outputs and Timing Preemphasis Digital Output Test Patterns SDIO Pin SCLK Pin CSB Pin RBIAS Pin VREF Pin GPOx Pins ADDRx Pins TX_TRIG± Pins Analog Test Tone Generation CW Doppler Operation Quadrature Generation I/Q Demodulator and Phase Shifter Digital RF Decimator Vector Profile RF Decimator DC Offset Calibration Multiband AAF and Decimate by 2 High-Pass Filter Digital Test Waveforms Waveform Generator Channel ID and Ramp Generator Digital Block Power Saving Scheme Serial Port Interface (SPI) Hardware Interface Memory Map Reading the Memory Map Table Reserved Locations Default Values Logic Levels Recommended Start-Up Sequence Memory Map Register Table Memory Map Register Descriptions Transfer (Register 0x0FF) Profile Index and Software TX_TRIG (Register 0x10C) Outline Dimensions Ordering Guide