Datasheet AD9234 (Analog Devices)

12-Bit, 1 GSPS/500 MSPS JESD204B, Dual Analog-to-Digital Converter Data Sheet AD9234 FEATURES FUNCTIONAL BLOCK DIAGRAM JESD204B (Subclass 1) coded serial digital outputs AVDD1 AVDD2 AVDD3 AVDD1_SR DVDD DRVDD SPIVDD (1.25V) (2.5V) (3.3V) (1.25V) (1.25V) (1.25V) (1.8V TO 3.3V) 1.5 W total power per channel at 1 GSPS (default settings) SFDR BUFFER + VIN+A ADC 12 ER 79 dBFS at 340 MHz (1 GSPS) VIN–A CORE IZ L DECIMATE 85 dBFS at 340 MHz (500 MSPS) IA TS FD_A BY 2 U 4 SERDOUT0± T CT TP SERDOUT1± SNR E SIGNAL D204B SER AS T SERDOUT2± MONITOR S F OU SERDOUT3± 63.4 dBFS at 340 MHz (A DE JE IN = −1.0 dBFS, 1 GSPS) FD_B DECIMATE Tx BY 2 SPEED 65.6 dBFS at 340 MHz (A 12 H IN = −1.0 dBFS, 500 MSPS) VIN+B ADC IG ENOB = 10.4 bits at 10 MHz (1 GSPS) VIN–B CORE H BUFFER DNL = ±0.16 LSB; INL = ±0.35 LSB (1 GSPS) FAST V_1P0 Noise density DETECT CLOCK SYNCINB± JESD204B −151 dBFS/Hz (1 GSPS) GENERATION SUBCLASS 1 AND ADJUST CONTROL SYSREF± −150 dBFS/Hz (500 MSPS) CLK+ 1.25 V, 2.5 V, and 3.3 V dc supply operation CLK– ÷2 SIGNAL SPI CONTROL ÷4 MONITOR PDWN/ Low swing full-scale input STBY ÷8 AD9234 1.34 V p-p typical (1 GSPS)
001
1.63 V p-p typical (500 MSPS) AGND DRGND DGND SDIO SCLK CSB
12244-
No missing codes
Figure 1.
Internal ADC voltage reference PRODUCT HIGHLIGHTS Flexible termination impedance
1. Low power consumption analog core, 12-bit, 1.0 GSPS dual
400 Ω, 200 Ω, 100 Ω, and 50 Ω differential
analog-to-digital converter (ADC) with 1.5 W per channel.
2 GHz usable analog input full power bandwidth
2.
95 dB channel isolation/crosstalk
Wide ful power bandwidth supports IF sampling of signals up to 2 GHz.
Amplitude detect bits for efficient AGC implementation Differential clock input
3. Buffered inputs with programmable input termination
Optional decimate by 2 DDC per channel
eases filter design and implementation.
Differential clock input
4. Flexible serial port interface (SPI) controls various product
Integer clock divide by 1, 2, 4, or 8
features and functions to meet specific system requirements.
Flexible JESD204B lane configurations
5. Programmable fast overrange detection.
Small signal dither
6. 9 mm × 9 mm 64-lead LFCSP. 7. Pin compatible with the AD9680 14-bit, 1 GSPS/500 MSPS
APPLICATIONS
dual ADC.
Communications Diversity multiband, multimode digital receivers 3G/4G, TD-SCDMA, W-CDMA, GSM, LTE Point to point radio systems Digital predistortion observation path General-purpose software radios Ultrawideband satellite receiver Instrumentation (spectrum analyzers, network analyzers, integrated RF test solutions) Digital oscilloscopes High speed data acquisition systems DOCSIS 3.0 CMTS upstream receive paths HFC digital reverse path receivers Rev. B Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties that may result from its use. Specifications subject to change without notice. No One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Tel: 781.329.4700 ©2014–2018 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. Technical Support www.analog.com
Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM PRODUCT HIGHLIGHTS TABLE OF CONTENTS REVISION HISTORY GENERAL DESCRIPTION SPECIFICATIONS DC SPECIFICATIONS AC SPECIFICATIONS DIGITAL SPECIFICATIONS SWITCHING SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL CHARACTERISTICS ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS AD9234-1000 AD9234-500 EQUIVALENT CIRCUITS THEORY OF OPERATION ADC ARCHITECTURE ANALOG INPUT CONSIDERATIONS Differential Input Configurations Input Common Mode Analog Input Controls and SFDR Optimization Absolute Maximum Input Swing VOLTAGE REFERENCE CLOCK INPUT CONSIDERATIONS Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust CLOCK JITTER CONSIDERATIONS POWER-DOWN/STANDBY MODE TEMPERATURE DIODE ADC OVERRANGE AND FAST DETECT ADC OVERRANGE FAST THRESHOLD DETECTION (FD_A AND FD_B) SIGNAL MONITOR SPORT Over JESD204B DIGITAL DOWNCONVERTER (DDC) DDC GENERAL DESCRIPTION HALF-BAND FILTER DDC GAIN STAGE DDC COMPLEX TO REAL CONVERSION DIGITAL OUTPUTS INTRODUCTION TO THE JESD204B INTERFACE JESD204B OVERVIEW FUNCTIONAL OVERVIEW Transport Layer Data Link Layer Physical Layer JESD204B LINK ESTABLISHMENT Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8B/10B Encoder PHYSICAL LAYER (DRIVER) OUTPUTS Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop CONFIGURING THE JESD204B LINK Example 1: Full Bandwidth Mode at 1 GSPS Example 2: Full Bandwidth Mode at 500 MSPS Example 3: ADC with DDC Option (Two ADCs Plus Two DDCs) DETERMINISTIC LATENCY SUBCLASS 0 OPERATION SUBCLASS 1 OPERATION Deterministic Latency Requirements Setting Deterministic Latency Registers MULTICHIP SYNCHRONIZATION NORMAL MODE TIMESTAMP MODE SYSREF± INPUT SYSREF± Control Features SYSREF± SETUP/HOLD WINDOW MONITOR LATENCY END TO END TOTAL LATENCY EXAMPLE LATENCY CALCULATION TEST MODES ADC TEST MODES JESD204B BLOCK TEST MODES Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes SERIAL PORT INTERFACE CONFIGURATION USING THE SPI HARDWARE INTERFACE SPI ACCESSIBLE FEATURES MEMORY MAP READING THE MEMORY MAP REGISTER TABLE Open and Reserved Locations Default Values Logic Levels Channel-Specific Registers SPI Soft Reset MEMORY MAP REGISTER TABLE APPLICATIONS INFORMATION POWER SUPPLY RECOMMENDATIONS EXPOSED PAD THERMAL HEAT SLUG RECOMMENDATIONS AVDD1_SR (PIN 57) AND AGND (PIN 56 AND PIN 60) OUTLINE DIMENSIONS ORDERING GUIDE