Datasheet AD9690 (Analog Devices) - 7

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Data Sheet AD9690 AD9690-500 AD9690-1000 Parameter1 Temperature Min Typ Max Min Typ Max Unit
WORST OTHER, EXCLUDING SECOND OR THIRD HARMONIC3 fIN = 10 MHz 25°C −95 −95 dBFS fIN = 170 MHz Full −95 −82 −94 −81 dBFS fIN = 340 MHz 25°C −93 −88 dBFS fIN = 450 MHz 25°C −93 −86 dBFS fIN = 765 MHz 25°C −88 −81 dBFS fIN = 985 MHz 25°C −89 −82 dBFS fIN = 1950 MHz 25°C −84 −75 dBFS TWO-TONE INTERMODULATION DISTORTION (IMD), AIN1 AND AIN2 = −7 dBFS fIN1 = 185 MHz, fIN2 = 188 MHz 25°C −88 −87 dBFS fIN1 = 338 MHz, fIN2 = 341 MHz 25°C −88 −88 dBFS FULL POWER BANDWIDTH4 25°C 2 2 GHz 1 See the AN-835 Application Note, Understanding High Speed ADC Testing and Evaluation, for definitions and for details on how these tests were completed. 2 Noise density is measured at a low analog input frequency (30 MHz). 3 See Table 10 for the recommended settings for ful -scale voltage and buffer current. 4 Measured with the circuit shown in Figure 64.
DIGITAL SPECIFICATIONS
AVDD1 = 1.25 V, AVDD2 = 2.5 V, AVDD3 = 3.3 V, AVDD1_SR = 1.25 V, DVDD = 1.25 V, DRVDD = 1.25 V, SPIVDD = 1.8 V, specified maximum sampling rate for each speed grade, AIN = −1.0 dBFS, clock divider = 2, default SPI settings, TA = 25°C, unless otherwise noted.
Table 3. Parameter Temperature Min Typ Max Unit
CLOCK INPUTS (CLK+, CLK−) Logic Compliance Full LVDS/LVPECL Differential Input Voltage Full 600 1200 1800 mV p-p Input Common-Mode Voltage Full 0.85 V Input Resistance (Differential) Full 35 kΩ Input Capacitance Full 2.5 pF SYSREF INPUTS (SYSREF+, SYSREF−) Logic Compliance Full LVDS/LVPECL Differential Input Voltage Full 400 1200 1800 mV p-p Input Common-Mode Voltage Full 0.6 0.85 2.0 V Input Resistance (Differential) Full 35 kΩ Input Capacitance (Differential) Full 2.5 pF LOGIC INPUTS (SDI, SCLK, CSB, PDWN/STBY) Logic Compliance Full CMOS Logic 1 Voltage Full 0.8 × SPIVDD V Logic 0 Voltage Full 0 0.2 × SPIVDD V Input Resistance Full 30 kΩ LOGIC OUTPUT (SDIO) Logic Compliance Full CMOS Logic 1 Voltage (IOH = 800 µA) Full 0.8 × SPIVDD V Logic 0 Voltage (IOL = 50 µA) Full 0.2 × SPIVDD V SYNCIN INPUT (SYNCINB+/SYNCINB−) Logic Compliance Full LVDS/LVPECL/CMOS Differential Input Voltage Full 400 1200 1800 mV p-p Input Common-Mode Voltage Full 0.6 0.85 2.0 V Input Resistance (Differential) Full 35 kΩ Input Capacitance Full 2.5 pF Rev. B | Page 7 of 78 Document Outline Features Applications Functional Block Diagram Product Highlights Revision History General Description Specifications DC Specifications AC Specifications Digital Specifications Switching Specifications Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Characteristics ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics AD9690-1000 AD9690-500 Equivalent Circuits Theory of Operation ADC Architecture Analog Input Considerations Differential Input Configurations Input Common Mode Analog Input Buffer Controls and SFDR Optimization Input Buffer Control Registers (0x018, 0x019, 0x01A, 0x935, 0x934, 0x11A) Absolute Maximum Input Swing Voltage Reference Clock Input Considerations Clock Duty Cycle Considerations Input Clock Divider Input Clock Divider ½ Period Delay Adjust Clock Fine Delay Adjust Clock Jitter Considerations Power-Down/Standby Mode Temperature Diode ADC Overrange and Fast Detect ADC Overrange Fast Threshold Detection (FD) Signal Monitor SPORT Over JESD204B Digital Downconverter (DDC) DDC I/Q Input Selection DDC I/Q Output Selection DDC General Description Frequency Translation General Description Variable IF Mode 0 Hz IF (ZIF) Mode fS/4 Hz IF Mode Test Mode DDC NCO Plus Mixer Loss and SFDR Numerically Controlled Oscillator Setting Up the NCO FTW and POW NCO Synchronization Mixer FIR Filters General Description Half-Band Filters HB4 Filter HB3 Filter HB2 Filter HB1 Filter DDC Gain Stage DDC Complex—Real Conversion DDC Example Configurations Digital Outputs Introduction to the JESD204B Interface JESD204B Overview Functional Overview Transport Layer Data Link Layer Physical Layer JESD204B Link Establishment Code Group Synchronization (CGS) and SYNCINB± Initial Lane Alignment Sequence (ILAS) User Data and Error Detection 8-Bit/10-Bit Encoder Physical Layer (Driver) Outputs Digital Outputs, Timing, and Controls De-Emphasis Phase-Locked Loop JESD204B Tx Converter Mapping Configuring the JESD204B Link Multichip Synchronization SYSREF± Setup/Hold Window Monitor Test Modes ADC Test Modes JESD204B Block Test Modes Transport Layer Sample Test Mode Interface Test Modes Data Link Layer Test Modes Serial Port Interface Configuration Using the SPI Hardware Interface SPI Accessible Features Memory Map Reading the Memory Map Register Table Open and Reserved Locations Default Values Logic Levels SPI Soft Reset Memory Map Register Table Applications Information Power Supply Recommendations Exposed Pad Thermal Heat Slug Recommendations AVDD1_SR (Pin 57) and AGND (Pin 56 and Pin 60) Outline Dimensions Ordering Guide