Datasheet AD4003-KGD (Analog Devices)

18-Bit, 2 MSPS Precision, Differential SAR ADC Known Good Die AD4003-KGD FEATURES GENERAL DESCRIPTION Throughput: 2 MSPS
The AD4003-KGD is a low noise, low power, high speed, 18-bit,
INL: ±1.0 LSB (±3.8 ppm) maximum
precision successive approximation register (SAR) analog-to-digital
Guaranteed 18-bit no missing codes
converter (ADC). The AD4003-KGD offers a 2 MSPS throughput.
Low power
The AD4003-KGD incorporates ease of use features that reduce
9.5 mW at 2 MSPS, 4.9 mW at 1 MSPS, 2.4 mW at 500 kSPS
signal chain power consumption and complexity, and enable higher
(VDD only)
channel density. The high-Z mode, coupled with a long acquisition
80 μW at 10 kSPS, 16 mW at 2 MSPS (total)
phase, eliminates the need for a dedicated high power, high speed
SNR: 100.5 dB typical at 1 kHz, VREF = 5 V; 99 dB typical at
ADC driver. Eliminating this ADC driver broadens the range of
100 kHz
low power, precision amplifiers that can drive this ADC directly,
THD: −123 dB typical at 1 kHz, VREF = 5 V; −100 dB typical at
while still achieving optimum performance. The input span com-
100 kHz
pression feature enables the ADC driver amplifier and the ADC to
Ease of use features reduce system power and complexity
operate off common supply rails without a negative supply, yet
Input overvoltage clamp circuit
preserves the full ADC code range. The low serial peripheral
Reduced nonlinear input charge kickback
interface (SPI) clock rate requirement reduces the digital input/
High-Z mode
output power consumption, broadens processor options, and
Long acquisition phase
simplifies the task of sending data across digital isolation.
Input span compression
Operating from a 1.8 V supply, the AD4003-KGD has a ±VREF fully
Fast conversion time allows low SPI clock rates
differential input range, with VREF ranging from 2.4 V to 5.1 V, and
SPI-programmable modes, read/write capability, status word
consumes 16 mW at 2 MSPS with a minimum SCK rate of 75 MHz
Differential analog input range: ±VREF
in turbo mode. The AD4003-KGD achieves ±1.0 LSB integral non-
0 V to VREF with VREF from 2.4 V to 5.1 V
linearty (INL) error maximum and guarantees no missing codes
Single 1.8 V supply operation with 1.71 V to 5.5 V logic interface
at 18 bits with 100.5 dB typical signal-to-noise ratio (SNR) for
SAR architecture: no latency/pipeline delay, valid first conversion
1 kHz inputs. The reference voltage is applied externally and can be
First conversion accurate
set independently of the supply voltage.
Guaranteed operation: −40°C to +125°C
The SPI-compatible, serial interface features seven modes, includ-
SPI-/QSPI-/MICROWIRE-/DSP-compatible serial interface
ing the ability, using the SDI input, to daisy-chain several ADCs on
Ability to daisy chain multiple ADCs and busy indicator
a single 3-wire bus and provides an optional busy indicator. The
APPLICATIONS
AD4003-KGD uses a simple SPI interface for writing to the config-
Automatic test equipment
uration register and receiving conversion results. The SPI interface
Machine automation
uses a separate supply, VIO, set to the host logic level. By using the
Medical equipment
VIO supply, the AD4003-KGD is compatible with 1.8 V, 2.5 V, 3 V,
Battery-powered equipment
and 5 V logic.
Precision data acquisition systems
Additional application and technical information can be found in the AD4003/AD4007/AD4011 data sheet. Known Good Die (KGD): these die are fully guaranteed to data sheet specifications.
FUNCTIONAL BLOCK DIAGRAM 2.5V TO 5V 10µF 1.8V REF VDD AD4003-KGD VIO VREF 1.8V TO 5V HIGH-Z V TURBO SDI REF/2 MODE MODE 0 IN+ SCK 18-BIT SERIAL 3-WIRE OR 4-WIRE INTERFACE SDO SAR ADC SPI INTERFACE V (DAISY CHAIN, CS) REF IN– STATUS CNV V CLAMP SPAN REF/2 COMPRESSION BITS
1
0
00 5-
GND
52 16 Figure 1.
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Document Outline Features Applications General Description Functional Block Diagram Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Description Outline Dimensions Die Specifications and Assembly Recommendations Ordering Guide