Datasheet AD4110-1 (Analog Devices) - 4

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AD4110-1 Data Sheet SPECIFICATIONS
VDD = +12 V to 20 V, VSS = −12 V to −20 V, AVDD5 = +5 V, IOVDD = +5 V, AGND = DGND = 0 V, VBIAS function = off, REFIN(+) = 2.5 V (external reference), REFIN(−) = 0 V, MCLK = 8 MHz (internal ADC clock), TA = −40°C to +105°C, all gains, unless otherwise noted.
Table 1. Parameter Min Typ Max Unit Test Conditions/Comments
HIGH VOLTAGE ANALOG INPUTS, AIN(±) Pins Differential Input Voltage Range, −VREF/Gain +VREF/Gain V For specified performance, gain > 0.2 Reference Voltage (VREF) ≤ 2.5 V −10 +10 V For specified performance, gain = 0.2 −12.5 +12.5 V Functional range, gain = 0.2 Absolute AIN Voltage VSS + 3 VDD − 3 V For specified performance Overvoltage Protection1, 2 AIN(+) – AGND, AIN(–) – AGND, ±30 V Using input resistor-capacitor (RC) low- AIN(+) – AIN(–) Pins pass filter with resistor (R) = 10 Ω, 0.5 W and capacitor (C) = 47 nF 50 V, VDD/VSS ≤ ±15 V VOLTAGE INPUT MODE Gain Error Before Calibration3 −1 +1 % TA = 25°C Using Calibration Coefficient4 −0.03 +0.03 % TA = 25°C, VDD/VSS = ±15 V Gain Drift vs. Temperature2 −3 +3 ppm/°C All gains except gain = 1 −8 +8 ppm/°C Gain = 1 Gain Drift vs. Time5 ±30 ppm Over 1000 hours Input Offset Error6 −350/Gain +350/Gain µV Gain = 0.2 to 3 −100 +100 µV Gain = 4 to 24 Input Offset Drift vs. Temperature2 2 14 µV/°C Gain = 0.2, referred to input 0.2 0.5 µV/°C Gain = 24, referred to input Input Offset Drift vs. Time5 ±50 µV Gain = 0.2, over 1000 hours ±25 µV Gain = 1, over 1000 hours ±4 µV Gain = 24, over 1000 hours Integral Nonlinearity 6 ppm/FSR Gain = 0.2, full-scale range (FSR) = 2 × full scale (FS) 25 75 ppm/FSR Gain = 24 Input Bias Current, AIN(+), AIN(−) Pins2 −0.5 +0.5 µA Input Bias Current, AIN(+) Pin −0.25 −0.15 −0.05 µA AIN(+) − AIN(−) < ±100 mV, AIN(−) = 0 V, VBIAS on/off, gain = 24, source impedance < 5 kΩ Input Bias Current Drift2 1 2.5 nA/°C AIN(+) and AIN(−) Input Offset Current2 −100 +100 nA Input Impedance7 >1 GΩ ΔVIN ÷ ΔIIN Input Voltage Noise and Resolution2 See Table 16 to Table 21 Input Common-Mode Rejection, DC 125 dB Gain = 24 100 dB Gain = 0.2 Input Common-Mode Rejection, AC 130 dB 50 Hz/60 Hz Power Supply Rejection, DC8 120 dB Related to VSS and VDD 83 dB Related to AVDD5, gain = 1, VIN = 1 V Normal Mode Rejection, 50 Hz/60 Hz 40 dB Sinc5 + sinc1 filter, ±0.5 Hz, external clock 100 dB Sinc3 filter, ±1 Hz Rev. 0 | Page 4 of 74 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION FUNCTIONAL BLOCK DIAGRAM TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS TIMING SPECIFICATIONS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION POWER SUPPLY SEQUENCE PROTECTION DIODE ANALOG INPUT PULL-UP/PULL-DOWN CURRENTS ANTIALIASING FILTER RTD EXCITATION CURRENTS FIELD POWER SUPPLY MODE NO POWER SUPPLY MODE BIAS VOLTAGE GENERATOR PGA CALIBRATION REGISTERS SERIAL INTERFACE CLOCK ADC ADC FILTER REGISTERS ADC GAIN AND OFFSET REGISTERS NOISE PERFORMANCE AND RESOLUTION MODES OF OPERATION DEFAULT MODE OF OPERATION ON POWER-UP CHANGING THE DEFAULT MODE OF OPERATION FOR FUTURE POWER-UP CYCLES POWER SUPPLY REQUIREMENTS SYSTEM CLOCK REQUIREMENTS BIPOLAR AND UNIPOLAR OUTPUT AUXILIARY LOW VOLTAGE INPUTS DIGITAL FILTER CONTINUOUS CONVERSION MODE INPUT AUTO SEQUENCING SINGLE CONVERSION MODE ADC CONVERSION DELAY BIAS VOLTAGE GENERATOR ANTIALIASING FILTER CIRCUIT CURRENT MODE Transimpedance Gain Using an External Sense Resistor VOLTAGE AND THERMOCOUPLE MODE Input Scaling for Voltage Mode Thermocouple Inputs RTD MODE Generating RTD Currents with an External Resistor Excitation Currents RTD Initial Drift 4-Wire RTD 3-Wire RTD 2-Wire RTD Alternative 3-Wire Configuration FIELD POWER SUPPLY MODE Overvoltage Protection NO POWER SUPPLY MODE Voltage Mode Current Mode System Redundancy GAIN CALIBRATION DATA REGISTER GAIN CALIBRATION IN VOLTAGE MODE GAIN CALIBRATION IN CURRENT MODE SCALING FACTOR AUTOCALIBRATION MODES APPLICATION EXAMPLES Example 1 Example 2 DIAGNOSTICS AND PROTECTION DIAGNOSTIC FLAGS ERROR PIN OVERTEMPERATURE DETECTION AND THERMAL SHUTDOWN OVERVOLTAGE AND UNDERVOLTAGE DETECTION OVERVOLTAGE PROTECTION DIAGNOSING OVERVOLTAGE AND UNDERVOLTAGE CONDITIONS OPEN WIRE DETECTION DIAGNOSTICS FOR RTD MEASUREMENTS AND RTD FLAGS NOISE, SETTLING TIME, AND DIGITAL FILTERING DIGITAL FILTER SINC5 + SINC1 FILTER SINC3 FILTER ENHANCED 50 HZ AND 60 HZ REJECTION FILTERS RTD MODE NOISE PERFORMANCE SERIAL PERIPHERAL INTERFACE RESETTING THE AD4110-1 SPI COMMAND TO COMMUNICATIONS REGISTER DOUT/ PIN WRITE OPERATION READ OPERATION MULTIPLE DEVICES ON THE SPI BUS CRC CHECKSUM CRC CHECKSUM METHODS Polynomial Calculation Polynomial CRC Calculation of a 24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation REGISTER DETAILS AFE REGISTER MAP AFE REGISTER DESCRIPTIONS AFE_TOP_STATUS Register AFE_CNTRL1 Register AFE_CLK_CTRL Register AFE_CNTRL2 Register PGA_RTD_CTRL Register AFE_ERR_DISABLE Register AFE_DETAIL_STATUS Register AFE_CAL_DATA Register AFE_RSENSE_DATA Register NO_PWR_DEFAULT_SEL Register NO_PWR_DEFAULT_STATUS Register ADC REGISTER MAP ADC REGISTER DESCRIPTIONS ADC_STATUS Register ADC_MODE Register ADC_INTERFACE Register ADC_CONFIG Register Data Register Filter Register ADC_GPIO_CONFIG Register ID Register ADC_OFFSET0 Register ADC_OFFSET1 Register ADC_OFFSET2 Register ADC_OFFSET3 Register ADC_GAIN0 Register ADC_GAIN1 Register ADC_GAIN2 Register ADC_GAIN3 Register OUTLINE DIMENSIONS ORDERING GUIDE