Datasheet AK5704 (Asahi Kasei Microdevices) - 9
| Fabricante | Asahi Kasei Microdevices |
| Descripción | Low-Power 4-ch 32-bit ADC with MIC-Amp |
| Páginas / Página | 109 / 9 — 6. Absolute Maximum Ratings. Parameter. Symbol. Min. Max. Unit. VSS1 and … |
| Formato / tamaño de archivo | PDF / 4.5 Mb |
| Idioma del documento | Inglés |
6. Absolute Maximum Ratings. Parameter. Symbol. Min. Max. Unit. VSS1 and VSS2 must be connected to the same analog ground plane
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6. Absolute Maximum Ratings
(VSS1 = VSS2 = 0 V; Note 3, Note 4)
Parameter Symbol Min. Max. Unit
Power Analog AVDD 0.3 4.3 V Supplies Digital I/F & LDO12 TVDD 0.3 4.3 V Input Current, Any Pin Except Supplies IIN - ±10 mA Analog Input Voltage (Note 5) VINA 0.3 4.3 V TVDD+0.3 Digital Input Voltage (Note 6) VIND1 0.3 V or 4.3 (Note 7) VIND2 0.3 AVDD+0.3 V Ambient Temperature (powered applied) Ta 40 85 C Storage Temperature Tstg 65 150 C Note 3. All voltages are with respect to ground. Note 4.
VSS1 and VSS2 must be connected to the same analog ground plane.
Note 5. AIN1A+/-, AIN1B+/-, AIN2A+/-, AIN2B+/- pins Note 6. MCKI, BCLK, LRCK, TDMIN, CAD, SCL, SDA, PDN pins; The maximum value is lower value between “TVDD+0.3V” and “4.3V”. Note 7. DMDAT1 and DMDAT2 pins WARNING: Operation beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(VSS1 = VSS2 = 0 V; Note 8)
Parameter Symbol Min. Typ. Max. Unit
Power Supplies AVDDL 1.7 1.8 1.9 V Analog (Note 9) AVDDH 3.0 3.3 3.6 V Digital I/F & LDO12 TVDD 1.65 1.8 3.6 V Note 8. All voltages are with respect to ground. Note 9. The power-up sequence between AVDD and TVDD is not critical. The PDN pin must be “L” upon power-up, and should be changed to “H” after all power supplies are supplied to avoid an internal circuit error. WARNING: AKM assumes no responsibility for the usage beyond the conditions in datasheet. 019000890-E-00 2019/02 - 9 - Document Outline 1. General Description 2. Features 3. Table of Contents 4. Block Diagram 5. Pin Configurations and Functions 5.1. Pin Configurations 5.2. Functions 5.3. Handling of Unused Pin 5.4. Pin State In Power-down Mode 6. Absolute Maximum Ratings 7. Recommended Operating Conditions 8. Electrical Characteristics 8.1. Microphone & ADC Analog Characteristics (AVDD=3.3V: AVDDL bit = “0”) 8.2. Microphone & ADC Analog Characteristics (AVDD=1.8V: AVDDL bit = “1”) 8.3. Power Supply Current 8.4. Power Consumption for Each Operation Mode 8.5. ADC1/2 Short Delay Sharp Roll-off Filter (ADVF bit = “0”) 8.6. ADC1/2 Digital Filter for Voice (ADVF bit = “1”) 8.7. DC Characteristics 8.8. Switching Characteristics 9. Functional Descriptions 9.1. Internal Pull-down Pin 9.2. LDO Circuit 9.3. System Clock 9.4. PLL 1. PLL Output Frequency (MCKO pin) 2. BCLK Output Frequency 3. Internal Block Diagram of PLL (3-1) PLL Reference Clock Divider (PLD) (3-2) PLL Feedback Clock Divider (PLM) 4. Adaptive Frequencies 5. Example of PLL Frequency Setting 9.5. Audio Interface Format 9.6. Synchronization with audio system (SYNCDET) 9.7. MIC/LINE Input 9.8. Microphone Amplifier Gain 9.9. Microphone Power 9.10. MIC Input Start-Up Time 9.11. ADC1/2 Initialization Cycle 9.12. Mono/Stereo Mode 9.13. Digital Microphone 9.14. Digital Block 9.14.1. Programmable Phase Adjustment 9.14.2. High Pass Filter (ADC1/2) 9.14.3. ADC1/2 Digital Filter 9.14.4. Microphone Sensitivity Adjustment 9.14.5. Monaural (MIX) Selection 9.14.6. High Pass Filter (HPF1/2) 9.14.7. Low Pass Filter (LPF1/2) 9.14.8. ALC Operation 9.14.9. Input Digital Volume (Manual Mode) 9.14.10. ALC 4ch Link Mode Sequence 9.15. Digital Voice Activity Detector 9.15.1. VDLY 9.15.2. HPF, LPF 9.15.3. ABS 9.15.4. NLD (Noise Level Detector) 9.15.5. MAX 9.15.6. MULT (X) 9.15.7. Comparator (>) 9.15.8. Guard Timer 9.15.9. Interrupt Output (WINTN pin) 9.15.10. Output Selector 9.16. I2C-bus Control Interface 9.17. Register Map 9.18. Register Definition 10. Recommended External Circuits 11. Control Sequence 11.1. Clock Set Up 11.1.1. PLL Master Mode 11.1.2. PLL Slave Mode (BCLK pin) 11.1.3. PLL Slave Mode (MCKI pin) 11.1.4. External Slave Mode 11.1.5. External Master Mode 11.2. Voice Activity Detection (1ch Mic) 11.3. Microphone Input Recording (4ch) 11.4. Stop of Clock 11.4.1. PLL Master Mode 11.4.2. PLL Slave Mode (BCLK pin) 11.4.3. PLL Slave Mode (MCKI pin) 11.4.4. External Slave Mode 11.4.5. External Master Mode 11.5. Power Down 12. Package 12.1. Outline Dimensions 12.2. Material & Lead finish 12.3. Marking 13. Ordering Guide 14. Revision History IMPORTANT NOTICE
6. Absolute Maximum Ratings
(VSS1 = VSS2 = 0 V; Note 3, Note 4)
Parameter Symbol Min. Max. Unit
Power Analog AVDD 0.3 4.3 V Supplies Digital I/F & LDO12 TVDD 0.3 4.3 V Input Current, Any Pin Except Supplies IIN - ±10 mA Analog Input Voltage (Note 5) VINA 0.3 4.3 V TVDD+0.3 Digital Input Voltage (Note 6) VIND1 0.3 V or 4.3 (Note 7) VIND2 0.3 AVDD+0.3 V Ambient Temperature (powered applied) Ta 40 85 C Storage Temperature Tstg 65 150 C Note 3. All voltages are with respect to ground. Note 4.
VSS1 and VSS2 must be connected to the same analog ground plane.
Note 5. AIN1A+/-, AIN1B+/-, AIN2A+/-, AIN2B+/- pins Note 6. MCKI, BCLK, LRCK, TDMIN, CAD, SCL, SDA, PDN pins; The maximum value is lower value between “TVDD+0.3V” and “4.3V”. Note 7. DMDAT1 and DMDAT2 pins WARNING: Operation beyond these limits may results in permanent damage to the device. Normal operation is not guaranteed at these extremes.
7. Recommended Operating Conditions
(VSS1 = VSS2 = 0 V; Note 8)
Parameter Symbol Min. Typ. Max. Unit
Power Supplies AVDDL 1.7 1.8 1.9 V Analog (Note 9) AVDDH 3.0 3.3 3.6 V Digital I/F & LDO12 TVDD 1.65 1.8 3.6 V Note 8. All voltages are with respect to ground. Note 9. The power-up sequence between AVDD and TVDD is not critical. The PDN pin must be “L” upon power-up, and should be changed to “H” after all power supplies are supplied to avoid an internal circuit error. WARNING: AKM assumes no responsibility for the usage beyond the conditions in datasheet. 019000890-E-00 2019/02 - 9 - Document Outline 1. General Description 2. Features 3. Table of Contents 4. Block Diagram 5. Pin Configurations and Functions 5.1. Pin Configurations 5.2. Functions 5.3. Handling of Unused Pin 5.4. Pin State In Power-down Mode 6. Absolute Maximum Ratings 7. Recommended Operating Conditions 8. Electrical Characteristics 8.1. Microphone & ADC Analog Characteristics (AVDD=3.3V: AVDDL bit = “0”) 8.2. Microphone & ADC Analog Characteristics (AVDD=1.8V: AVDDL bit = “1”) 8.3. Power Supply Current 8.4. Power Consumption for Each Operation Mode 8.5. ADC1/2 Short Delay Sharp Roll-off Filter (ADVF bit = “0”) 8.6. ADC1/2 Digital Filter for Voice (ADVF bit = “1”) 8.7. DC Characteristics 8.8. Switching Characteristics 9. Functional Descriptions 9.1. Internal Pull-down Pin 9.2. LDO Circuit 9.3. System Clock 9.4. PLL 1. PLL Output Frequency (MCKO pin) 2. BCLK Output Frequency 3. Internal Block Diagram of PLL (3-1) PLL Reference Clock Divider (PLD) (3-2) PLL Feedback Clock Divider (PLM) 4. Adaptive Frequencies 5. Example of PLL Frequency Setting 9.5. Audio Interface Format 9.6. Synchronization with audio system (SYNCDET) 9.7. MIC/LINE Input 9.8. Microphone Amplifier Gain 9.9. Microphone Power 9.10. MIC Input Start-Up Time 9.11. ADC1/2 Initialization Cycle 9.12. Mono/Stereo Mode 9.13. Digital Microphone 9.14. Digital Block 9.14.1. Programmable Phase Adjustment 9.14.2. High Pass Filter (ADC1/2) 9.14.3. ADC1/2 Digital Filter 9.14.4. Microphone Sensitivity Adjustment 9.14.5. Monaural (MIX) Selection 9.14.6. High Pass Filter (HPF1/2) 9.14.7. Low Pass Filter (LPF1/2) 9.14.8. ALC Operation 9.14.9. Input Digital Volume (Manual Mode) 9.14.10. ALC 4ch Link Mode Sequence 9.15. Digital Voice Activity Detector 9.15.1. VDLY 9.15.2. HPF, LPF 9.15.3. ABS 9.15.4. NLD (Noise Level Detector) 9.15.5. MAX 9.15.6. MULT (X) 9.15.7. Comparator (>) 9.15.8. Guard Timer 9.15.9. Interrupt Output (WINTN pin) 9.15.10. Output Selector 9.16. I2C-bus Control Interface 9.17. Register Map 9.18. Register Definition 10. Recommended External Circuits 11. Control Sequence 11.1. Clock Set Up 11.1.1. PLL Master Mode 11.1.2. PLL Slave Mode (BCLK pin) 11.1.3. PLL Slave Mode (MCKI pin) 11.1.4. External Slave Mode 11.1.5. External Master Mode 11.2. Voice Activity Detection (1ch Mic) 11.3. Microphone Input Recording (4ch) 11.4. Stop of Clock 11.4.1. PLL Master Mode 11.4.2. PLL Slave Mode (BCLK pin) 11.4.3. PLL Slave Mode (MCKI pin) 11.4.4. External Slave Mode 11.4.5. External Master Mode 11.5. Power Down 12. Package 12.1. Outline Dimensions 12.2. Material & Lead finish 12.3. Marking 13. Ordering Guide 14. Revision History IMPORTANT NOTICE