Datasheet ADRF6520 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | Dual Programmable Filters and VGAs for 2 GHz Channel Spacing for μW Radios |
| Páginas / Página | 29 / 8 — ADRF6520. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. +85°C. +25°C. … |
| Formato / tamaño de archivo | PDF / 1.6 Mb |
| Idioma del documento | Inglés |
ADRF6520. Data Sheet. TYPICAL PERFORMANCE CHARACTERISTICS. +85°C. +25°C. –40°C. B) d. R (. d N (. RRO. N E AI G. –10. 0.25. 0.50. 0.75. 1.00. 1.25. 1.50
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ADRF6520 Data Sheet TYPICAL PERFORMANCE CHARACTERISTICS
VPS, VPSD = 3.3 V, TA = 25°C, ZLOAD = 100 Ω, dc offset correction loop disable bit (B5) = 1 (enabled), noise spectral density (NSD) measured at fC/2 and at 500 MHz in bypass mode, unless otherwise noted. Noise figure measured with 100 Ω differential input termination. Worst case IMD3 tone is reported for al IMD3/IP3 plots.
25 3 +85°C +85°C +25°C +25°C –40°C –40°C 20 2 15 1 B) d B) 10 R ( d N ( 0 RRO AI 5 G N E AI G –1 0 –2 –5 –10 –3 0 0.25 0.50 0.75 1.00 1.25 1.50
003
0 0.25 0.50 0.75 1.00 1.25 1.50
006
VGN1 (V)
14830-
VGN1 (V)
14830- Figure 3. Gain at 500 MHz vs. VGN1 over Temperature; Bypass Mode, Figure 6. Gain Error at 500 MHz vs. VGN1 over Temperature; Bypass Mode, VGN2 = 0 V VGN2 = 0 V
60 5 +85°C +85°C +25°C +25°C 4 –40°C –40°C 3 50 2 B) d 1 B) R ( d 40 N ( 0 RRO AI G N E –1 AI G –2 30 –3 –4 20 –5
007
0 0.25 0.50 0.75 1.00 1.25 1.50
004
0 0.25 0.50 0.75 1.00 1.25 1.50 VGN2 (V) VGN2 (V)
14830- 14830- Figure 4. Gain at 500 MHz vs. VGN2 over Supply; Bypass Mode, Figure 7. Gain Error at 500 MHz vs. VGN2 over Temperature; Bypass Mode, VGN1 = 1.5 V VGN1 = 1.5 V
25 60 3.15V 3.15V 3.45V 3.45V 3.3V 3.3V 20 50 15 B) 10 B) d d N ( 40 N ( AI AI 5 G G 0 30 –5 –10 20 0 0.25 0.50 0.75 1.00 1.25 1.50
103
0 0.25 0.50 0.75 1.00 1.25 1.50
104
VGN1 (V)
14830-
VGN2 (V)
14830- Figure 5. Gain at 500 MHz vs. VGN1 over Supply; Bypass Mode, Figure 8. Gain at 500 MHz vs. VGN2 over Supply; Bypass Mode, VGN2 = 0 V VGN1 = 1.5 V Rev. 0 | Page 8 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT VGAs RMS DETECTOR PROGRAMMABLE FILTERS Bypassing the Filters VARIABLE GAIN AMPLIFIERS OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE ADRF6520 NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS SPI REGISTER AND TIMING REGISTER READ/WRITE TIMING Write Cycle Read Cycle APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION GAIN PIN DECOUPLING RMS DETECTOR CONNECTIONS VGA2 GAIN STEP RESPONSE LINEAR OPERATION OF THE ADRF6520 EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE
VPS, VPSD = 3.3 V, TA = 25°C, ZLOAD = 100 Ω, dc offset correction loop disable bit (B5) = 1 (enabled), noise spectral density (NSD) measured at fC/2 and at 500 MHz in bypass mode, unless otherwise noted. Noise figure measured with 100 Ω differential input termination. Worst case IMD3 tone is reported for al IMD3/IP3 plots.
25 3 +85°C +85°C +25°C +25°C –40°C –40°C 20 2 15 1 B) d B) 10 R ( d N ( 0 RRO AI 5 G N E AI G –1 0 –2 –5 –10 –3 0 0.25 0.50 0.75 1.00 1.25 1.50
003
0 0.25 0.50 0.75 1.00 1.25 1.50
006
VGN1 (V)
14830-
VGN1 (V)
14830- Figure 3. Gain at 500 MHz vs. VGN1 over Temperature; Bypass Mode, Figure 6. Gain Error at 500 MHz vs. VGN1 over Temperature; Bypass Mode, VGN2 = 0 V VGN2 = 0 V
60 5 +85°C +85°C +25°C +25°C 4 –40°C –40°C 3 50 2 B) d 1 B) R ( d 40 N ( 0 RRO AI G N E –1 AI G –2 30 –3 –4 20 –5
007
0 0.25 0.50 0.75 1.00 1.25 1.50
004
0 0.25 0.50 0.75 1.00 1.25 1.50 VGN2 (V) VGN2 (V)
14830- 14830- Figure 4. Gain at 500 MHz vs. VGN2 over Supply; Bypass Mode, Figure 7. Gain Error at 500 MHz vs. VGN2 over Temperature; Bypass Mode, VGN1 = 1.5 V VGN1 = 1.5 V
25 60 3.15V 3.15V 3.45V 3.45V 3.3V 3.3V 20 50 15 B) 10 B) d d N ( 40 N ( AI AI 5 G G 0 30 –5 –10 20 0 0.25 0.50 0.75 1.00 1.25 1.50
103
0 0.25 0.50 0.75 1.00 1.25 1.50
104
VGN1 (V)
14830-
VGN2 (V)
14830- Figure 5. Gain at 500 MHz vs. VGN1 over Supply; Bypass Mode, Figure 8. Gain at 500 MHz vs. VGN2 over Supply; Bypass Mode, VGN2 = 0 V VGN1 = 1.5 V Rev. 0 | Page 8 of 29 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION INPUT VGAs RMS DETECTOR PROGRAMMABLE FILTERS Bypassing the Filters VARIABLE GAIN AMPLIFIERS OUTPUT BUFFERS/ADC DRIVERS DC OFFSET COMPENSATION LOOP PROGRAMMING THE ADRF6520 NOISE CHARACTERISTICS DISTORTION CHARACTERISTICS MAXIMIZING THE DYNAMIC RANGE KEY PARAMETERS FOR QUADRATURE-BASED RECEIVERS SPI REGISTER AND TIMING REGISTER READ/WRITE TIMING Write Cycle Read Cycle APPLICATIONS INFORMATION BASIC CONNECTIONS SUPPLY DECOUPLING INPUT SIGNAL PATH OUTPUT SIGNAL PATH DC OFFSET COMPENSATION LOOP ENABLED SERIAL PORT CONNECTIONS ENABLE/DISABLE FUNCTION GAIN PIN DECOUPLING RMS DETECTOR CONNECTIONS VGA2 GAIN STEP RESPONSE LINEAR OPERATION OF THE ADRF6520 EVALUATION BOARD OUTLINE DIMENSIONS ORDERING GUIDE