Datasheet ADL5335 (Analog Devices) - 4

FabricanteAnalog Devices
Descripción700 MHz to 4200 MHz Tx DGA
Páginas / Página16 / 4 — ADL5335. Data Sheet. Parameter. Test Conditions/Comments. Min. Typ. Max. …
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ADL5335. Data Sheet. Parameter. Test Conditions/Comments. Min. Typ. Max. Unit

ADL5335 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit

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ADL5335 Data Sheet Parameter Test Conditions/Comments Min Typ Max Unit
BAND 1: 2110 MHz TO 2170 MHz Gain Range 20 dB Maximum Gain 12.5 dB Minimum Gain −7.5 dB Gain Flatness ±200 MHz, all gains 0.5 dB Gain Step Error All gain states 0.38 dB Group Delay Variation Between any attenuation step 20 ps Output IP3 Maximum gain, 4 dBm per tone 32 dBm Minimum gain, −18 dBm per tone 11.6 dBm Output P1dB Maximum gain 18.1 dBm Minimum gain −0.2 dBm Noise Figure Maximum gain 6.9 dB Minimum gain 10.4 dB Return Loss Input −32 dB Output Minimum gain −25 dB Maximum gain −19 dB CMRR vs. frequency (±200 MHz) 25 dB BAND 7: 2620 MHz TO 2690 MHz Gain Range 20 dB Maximum Gain 12.0 dB Minimum Gain −8.0 dB Gain Flatness ±200 MHz, all gains 0.7 dB Gain Step Error All gain states 0.37 dB Group Delay Variation Between any attenuation step 30 ps Output IP3 Maximum gain, 4 dBm per tone 32 dBm Minimum gain, −18 dBm per tone 13.1 dBm Output P1dB Maximum gain 17.8 dBm Minimum gain −1.1 dBm Noise Figure Maximum gain 7.5 dB Minimum gain 10.5 dB Return Loss Input −19 dB Output Minimum gain −24 dB Maximum gain −17 dB CMRR vs. frequency (±200 MHz) 26 dB BAND 42: 3400 MHz TO 3600 MHz Gain Range 20 dB Maximum Gain 10.2 dB Minimum Gain −9.8 dB Gain Flatness ±200 MHz, all gains 0.7 dB Gain Step Error All gain states 0.36 dB Group Delay Variation Between any attenuation step 20 ps Output IP3 Maximum gain, 4 dBm per tone 31 dBm Minimum gain, −18 dBm per tone 10.9 dBm Output P1dB Maximum gain 16.8 dBm Minimum gain 2.3 dBm Noise Figure Maximum gain 7.5 dB Minimum gain 12.2 dB Rev. 0 | Page 4 of 16 Document Outline FEATURES APPLICATIONS FUNCTIONAL BLOCK DIAGRAM GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS DIGITAL LOGIC TIMING SPI Timing Diagram ABSOLUTE MAXIMUM RATINGS THREMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION BASIC STRUCTURE DIGITAL INTERFACE OVERVIEW Serial Peripheral Interface (SPI) Fast Attack (FA) APPLICATIONS INFORMATION BASIC CONNECTIONS OUTLINE DIMENSIONS ORDERING GUIDE