Datasheet AD7490-EP (Analog Devices) - 7

Enhanced Product AD7490-EP PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VIN11 1 28 VIN12 VIN10 2 27 VIN13 VIN9 3 26 VIN14 NC 4 25 VIN15 VIN8 5 24 AGND AD7490-EP VIN7 6 23 REF TOP VIEW IN VIN6 7 (Not to Scale) 22 VDD VIN5 8 21 AGND VIN4 9 20 CS VIN3 10 19 DIN VIN2 11 18 NC VIN1 12 17 VDRIVE VIN0 13 16 SCLK AGND 14 15 DOUT NC = NO CONNECT
3 0
ALL NC PINS SHOULD BE
-0 36
CONNECTED STRAIGHT TO AGND
89 0 Figure 3. 28-Lead TSSOP Pin Configuration
Table 4. Pin Function Descriptions Pin No. Mnemonic Description
20 CS Chip Select. Active low logic input. This input provides the dual function of initiating conversions on the AD7490-EP and also frames the serial data transfer. 23 REFIN Reference Input for the AD7490-EP. An external reference must be applied to this input. The voltage range for the external reference is 2.5 V ± 1% for specified performance. 22 VDD Power Supply Input. The VDD range for the AD7490-EP is from 2.7 V to 5.25 V. For the 0 V to 2 × REFIN range, VDD should be from 4.75 V to 5.25 V. 14, 21, AGND Analog Ground. Ground reference point for all circuitry on the AD7490-EP. All analog/digital input signals and any 24 external reference signal should be referred to this AGND voltage. All AGND pins should be connected together. 13 to 5, VIN0 to Analog Input 0 through Analog Input 15. Sixteen single-ended analog input channels that are multiplexed into 3 to 1, VIN15 the on chip track-and-hold. The analog input channel to be converted is selected by using the address bits ADD3 28 to 25 through ADD0 of the control register. The address bits, in conjunction with the SEQ and SHADOW bits, allow the sequence register to be programmed. The input range for all input channels can extend from 0 V to REFIN or 0 V to 2 × REFIN as selected via the RANGE bit in the control register. Any unused input channels should be connected to AGND to avoid noise pickup. 19 DIN Data In. Logic input. Data to be written to the control register of the AD7490-EP is provided on this input and is clocked into the register on the falling edge of SCLK (see the AD7490 data sheet). 15 DOUT Data Out. Logic output. The conversion result from the AD7490-EP is provided on this output as a serial data stream. The bits are clocked out on the falling edge of the SCLK input. The data stream consists of four address bits indicating which channel the conversion result corresponds to, followed by the 12 bits of conversion data, which is provided by MSB first. The output coding can be selected as straight binary or twos complement via the CODING bit in the control register. 16 SCLK Serial Clock. Logic input. SCLK provides the serial clock for accessing data from the part. This clock input is also used as the clock source for the conversion process of the AD7490-EP. 17 VDRIVE Logic Power Supply Input. The voltage supplied at this pin determines at what voltage the serial interface of the AD7490-EP operates. Rev. B | Page 7 of 12 Document Outline Features Enhanced Product Features Functional Block Diagram General Description Product Highlights Revision History Specifications Timing Specifications Absolute Maximum Ratings ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Outline Dimensions Ordering Guide