Datasheet LTC1863, LTC1867 (Analog Devices) - 5

FabricanteAnalog Devices
Descripción16-Bit, 8-Channel 200ksps ADCs
Páginas / Página18 / 5 — POWER REQUIREMENTS The. denotes the specifications which apply over the …
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POWER REQUIREMENTS The. denotes the specifications which apply over the full operating temperature

POWER REQUIREMENTS The denotes the specifications which apply over the full operating temperature

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LTC1863/LTC1867
POWER REQUIREMENTS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC1863/LTC1867/LTC1867A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
VDD Supply Voltage (Note 9) 4.75 5.25 V IDD Supply Current fSAMPLE = 200ksps l 1.3 1.8 mA NAP Mode 150 µA SLEEP Mode l 0.2 3 µA PDISS Power Dissipation l 6.5 9 mW
TIMING CHARACTERISTICS The
l
denotes the specifications which apply over the full operating temperature range, otherwise specifications are at TA = 25°C. (Note 5) LTC1863/LTC1867/LTC1867A SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS
fSAMPLE Maximum Sampling Frequency l 200 kHz tCONV Conversion Time l 3 3.5 µs tACQ Acquisition Time l 1.5 1.1 µs fSCK SCK Frequency 40 MHz t1 CS/CONV High Time Short CS/CONV Pulse Mode l 40 100 ns t2 SDO Valid After SCK↓ CL = 25pF (Note 11) l 13 22 ns t3 SDO Valid Hold Time After SCK↓ CL = 25pF l 5 11 ns t4 SDO Valid After CS/CONV↓ CL = 25pF l 10 30 ns t5 SDI Setup Time Before SCK↑ l 15 –6 ns t6 SDI Hold Time After SCK↑ l 10 4 ns t7 SLEEP Mode Wake-Up Time CREFCOMP = 10µF, CVREF = 2.2µF 60 ms t8 Bus Relinquish Time After CS/CONV↑ CL = 25pF l 20 40 ns
Note 1:
Stresses beyond those listed under Absolute Maximum Ratings
Note 7:
Integral nonlinearity is defined as the deviation of a code from a may cause permanent damage to the device. Exposure to any Absolute straight line passing through the actual endpoints of the transfer curve. Maximum Rating condition for extended periods may affect device The deviation is measured from the center of the quantization band. reliability and lifetime
Note 8:
Unipolar offset is the offset voltage measured from +1/2LSB
Note 2:
All voltage values are with respect to GND (unless otherwise noted). when the output code flickers between 0000 0000 0000 0000 and
Note 3:
When these pin voltages are taken below GND or above VDD, they 0000 0000 0000 0001 for LTC1867 and between 0000 0000 0000 and will be clamped by internal diodes. This product can handle input currents 0000 0000 0001 for LTC1863. Bipolar offset is the offset voltage measured up to 100mA without latchup. from –1/2LSB when output code flickers between 0000 0000 0000 0000
Note 4:
When these pin voltages are taken below GND, they will be and 1111 1111 1111 1111 for LTC1867, and between clamped by internal diodes. This product can handle input currents up to 0000 0000 0000 and 1111 1111 1111 for LTC1863. 100mA below GND without latchup. These pins are not clamped to VDD.
Note 9:
Recommended operating conditions. The input range of ±2.048V
Note 5:
V for bipolar mode is measured with respect to V DD = 5V, fSAMPLE = 200ksps at 25°C, tr = tf = 5ns and IN– = 2.5V. VIN– = 2.5V for bipolar mode unless otherwise specified.
Note 10:
Guaranteed by design, not subject to test.
Note 6:
Linearity, offset and gain error specifications apply for both
Note 11:
t2 of 25ns maximum allows fSCK up to 20MHz for rising capture unipolar and bipolar modes. The INL and DNL are tested in bipolar mode. with 50% duty cycle and fSCK up to 40MHz for falling capture (with 3ns setup time for the receiving logic). Rev. E For more information www.analog.com 5 Document Outline Features Applications Block Diagram Description Absolute Maximum Ratings Order Information Pin Configuration Converter Characteristics Dynamic Accuracy Analog Input Internal Reference Characteristics Digital Inputs and Digital Outputs Power Requirements Timing Characteristics Typical Performance Characteristics Pin Functions Typical Connection Diagram Test Circuits Timing Diagrams Applications Information Package Description Revision History Related Parts