Key Sheet AD7193 (Analog Devices) - 3

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Key Sheet AD7193 OPERATING THE AD7193 DATA INTERFACE Table 5. 3-Wire Serial Interface Pin Functions
The data interface for the AD7193 is
Pin Function
CS CS is permanently tied low in the 3-wire interface. • Performed using a 4- or 3-wire SPI (If CS is required as a decoding signal, it can be • Compatible with QSPI, MICROWIRE, and DSP generated from a port pin.) • Al ows a user to both write to and read from the AD7193 SCLK Determines when data transfers (either on DIN or on the same data bus DOUT/RDY) occur. • Indicates when transferred data is available by bringing the DOUT/RDY Accesses data from the on-chip registers. DOUT/RDY signal and the RDY bit in the status register low Indicates when the transferred data is available. DIN Transfers data into the on-chip registers.
4-Wire Serial Interface AD7193 DATA MODES (SLAVE)
There are three data modes available: continuous conversion
CS
mode, continuous read mode, and single conversion mode.
SCLK Continuous Conversion Mode (Default) DSP/FPGA/ MICROCONTROLLER
Continuous conversion is the default power-up mode. In this
DOUT/RDY
mode, the AD7193 converts continuously, and the RDY bit in
DIN
the status register goes low each time a conversion is complete. If CS is low, the DOUT/RDY line also goes low when a conversion Figure 2. AD7193 Data Interface, 4-Wire SPI is complete. To read a conversion, the user writes to the
Table 4. 4-Wire Serial Interface Pin Functions
communications register, indicating that the next operation is a read of the data register. When the data-word has been read from
Pin Function
the data register, DOUT/RDY goes high. The user can read this CS Selects the ADC (also applicable in systems with multiple devices on the serial bus). register additional times, if required. Provides a frame synchronization signal.1 When several channels are enabled, the ADC continuously SCLK Determines when data transfers (either on DIN or loops through the enabled channels, performing one conversion DOUT/RDY) occur. on each channel per loop. The data register is updated as soon DOUT/RDY Accesses data from the on-chip registers. as each conversion is available. The DOUT/RDY pin pulses low Indicates when the transferred data is available. each time a conversion is available. The user can then read the DIN Transfers data into the on-chip registers. conversion while the ADC converts on the next enabled channel. 1 Useful for DSP interfaces. The first bit (MSB) is effectively clocked out by CS
CS
because CS typically occurs after the falling edge of SCLK in DSPs. The SCLK can continue to run between data transfers, provided the timing numbers are obeyed.
DATA DATA DIN REQUEST REQUEST 3-Wire Serial Interface DATA DOUT/RDY DATA AD7193 (SLAVE) CS (TIED LOW) SCLK
Figure 4. Continuous Conversion Mode
SCLK DSP/FPGA/ MICROCONTROLLER DOUT/RDY DIN
Figure 3. AD7193 Data Interface, 3-Wire SPI Rev. 0 | Page 3 of 6 Document Outline General Description Features and Benefits Key Characteristics Fundamental Specifications Noise Sinc4 Chop Disabled Filter Setting Fast Settling Filter Setting Operating the AD7193 Data Interface 4-Wire Serial Interface 3-Wire Serial Interface Data Modes Continuous Conversion Mode (Default) Continuous Read Mode Single Conversion Mode Typical Application Diagram Frequently Asked Questions Learn More and Start Designing Compatible Devices Package Diagram Getting Started