Datasheet ADAR7251 (Analog Devices) - 8

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ADAR7251 Data Sheet DIGITAL FILTER Table 4. Parameter Mode Factor Min Typ Max Unit
ADC DECIMATION FILTER At fS =1.2 MHz, decimation ratio = 48 At fS = 1.2 MHz, Decimation Ratio = 48 Pass Band −0.1 dB corner 0.166 × fS 200 kHz Pass-Band Droop At 600 kHz −1.4 dB Stop Band 0.666 × fS 800 kHz Stop-Band Attenuation 70 dB Group Delay 95 μs High-Pass Filter Corner Frequency −3 dB, programmable in eight steps 0.729 93.3 Hz Attenuation See Figure 24 in the Typical Performance Characteristics section
SPI PORT TIMING
DVDDx = 1.8 V, IOVDDx = 3.3 V, C LOAD = 22 pF, IOUT = ±1 mA.
Table 5. Limit at Parameter Description Min Typ Max Unit
SPI PORT See Figure 2 tCCPH SPI_SCLK high 50 ns tCCPL SPI_SCLK low 50 ns fSPI_CLK SPI_SCLK frequency 10 MHz tCDS SPI_MOSI setup to SPI_SCLK rising 10 ns tCDH SPI_MOSI hold from SPI_SCLK rising 10 ns tCLS SPI_SS setup to SPI_SCLK rising 10 ns tCLH SPI_SS hold from SPI_SCLK rising 40 ns tCLPH SPI_SS high 10 ns tCDH SPI_MISO hold from SPI_SCLK rising 30 ns tCOD SPI_MISO delay from SPI_SCLK falling 30 ns tCOTS SPI_MISO tristate from SPI_SS rising 30 ns
SERIAL/PERIPHERAL PARALLEL INTERFACE (PPI) PORT TIMING
DVDDx = 1.8 V, IOVDDx = 3.3 V, C LOAD = 22 pF, IOUT = ±1 mA.
Table 6. Limit at Parameter Description Min Typ Max Unit
INPUT MASTER CLOCK (MCLKIN) Duty Cycle MCLKIN duty cycle; MCLKIN at 256 × fS, 384 × fS, 512 × fS, and 768 × fS 40 60 % fMCLKIN MCLKIN frequency, PLL in MCLK mode 16 54 MHz RESET Reset Pulse, tRESET RESET/PWDN held low 15 ns PLL Lock Time 1 ms Rev. 0 | Page 8 of 72 Document Outline Features Applications General Description Revision History Functional Block Diagram Specifications Analog Channel Digital Input/Output Power Supply Digital Filter SPI Port Timing Serial/Peripheral Parallel Interface (PPI) Port Timing Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Terminology Theory of Operation Low Speed Ramp Radar Analog Front End Main Channel Overview Σ-∆ Modulation and Digital Filtering Differential Input Configuration High-Pass Filter (HPF) Low-Pass Filter (LPF) Input Routing Equalizer (EQ) Using LNA/PGA, EQ, or the Input Capacitor Reference Auxiliary ADC Power Supply LDO Clock Requirements Crystal Oscillator PLL Integer Mode Fractional Mode PLL Lock Acquisition GPIO ADC Data Port ADC Serial Mode ADC Serial Master Mode ADC Serial Master Mode with ADC Serial Slave ADC PPI (Byte Wide Mode) ADC PPI Nibble Wide Mode DAQ Mode Using Multiple ADAR7251 Devices for Systems with More Than Four Channels Device Address R/ Register Address Data Bytes CRC PCB Layout Guidelines Register Summary Register Details Clock Control Register PLL Denominator Register PLL Numerator Register PLL Control Register PLL Status Register Master Enable Switch Register ADC Enable Register Power Enable Register Clear the ASIL errors Register Selects Which Errors to Mask Register ASIL Error Flag Register ASIL Error Code Register CRC Value, Bits[7:0] Register CRC Value Register Start Calculating the CRC Value of the Register Map Content Register Register Map CRC Calculation Done Register Register Map CRC Value, Bits[7:0] Register Register Map CRC Value, Bits[15:8] Register Low Noise Amplifier Gain Control Register Programmable Gain Amplifier Gain Control Register Signal Path for ADC 1 Through ADC 4 Register Decimator Rate Control Register High Pass Filter Control Register DAQ Mode Control Register Decimator Truncate Control Register Serial Output Port Control Register Parallel Port Control Register ADC Digital Output Mode Register Auxiliary ADC Read Value Registers Auxiliary ADC Sample Rate Selection Register Auxiliary ADC Mode Register MPx Pin Modes Registers MP Write Value Registers MP Read Value Registers SPI_CLK Pin Drive Strength and Slew Rate Register SPI_MISO Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register SPI_MOSI Pin Drive Strength and Slew Rate Register ADDR15 Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register FS_ADC Pin Drive Strength and Slew Rate Register Pin Drive Strength and Slew Rate Register SCLK_ADC Pin Drive Strength and Slew Rate Register ADC_DOUTx Pins Drive Strength and Slew Rate Registers DATA_READY Pin Drive Strength and Slew Rate Register XTAL Enable and Drive Register ADC Test Register Digital Filter Sync Enable Register CRC Enable/Disable Register Typical Application Circuit Outline Dimensions Ordering Guide Automotive Products