Datasheet A4975 (Allegro) - 7

A4975 Full-Bridge PWM Microstepping Motor Driver Functional Description
age the current-sense comparator resets the PWM latch, which turns off the source drivers (slow decay mode) or the sink and Two A4975 full-bridge PWM microstepping motor drivers are source drivers (fast- or mixed decay mode). needed to drive the windings of a bipolar stepper motor. Inter- nal pulse width modulated (PWM) control circuitry regulates With the DAC data input lines at VIN(1) voltage, the maximum each motor winding current. The peak motor current is set by value of current limiting is set by the selection of RS and VREF the value of an external current-sense resistor (RS), a reference with a transconductance function approximated by: voltage (VREF), and the digital-to-analog converter (DAC) data I inputs (D TRIP ≈ VREF / 5RS. 0, D1, and D2). The actual peak load current (I To improve motor performance, especially when using sinusoi- PEAK) will be slightly higher than I dal current profiles necessary for microstepping, the A4975 has TRIP due to internal logic and switching delays. The driver(s) remain off for a time period determined by a user-selected three distinct current decay modes: slow decay, fast decay, and external resistor-capacitor combination (R mixed decay. TCT). At the end of the fixed off-time, the driver(s) are re-enabled, allowing the load
PHASE Input.
The PHASE input controls the direction of current to increase to ITRIP again, maintaining an average load current flow in the load (table 1). An internally generated dead current. time of approximately 500 ns prevents crossover currents that The DAC data input lines are used to provide up to eight levels could occur when switching the PHASE input. of output current. The internal 3-bit digital-to-analog converter
DAC Data Inputs (D
reduces the reference input to the current-sense comparator
0, D1, D2).
A non-linear DAC is used to digitally control the output current. The output of the DAC is in precise steps (the step reference current ratio or SRCR) to used to set the trip point of the current-sense comparator. Table 3 provide half-step, quarter-step, or “microstepping” load-current shows DAC output voltages for each input condition. When D levels. 0, D1, and D2 are all logic low, all of the power output transistors ITRIP ≈ SRCR × VREF / 5RS are turned off.
Slow Current Decay Mode.
When V
Internal PWM Current Control.
PFD ≥ 3.5 V, the Each motor driver device is in slow current decay mode (the source drivers are contains an internal fixed off-time PWM current control circuit disabled when the load current reaches ITRIP). During the fixed that limits the load current to a desired value (ITRIP). Initially, a off-time, the load inductance causes the current to recirculate diagonal pair of source and sink transistors are enabled and cur- through the motor winding and sink drivers (see figure 1). Slow rent flows through the motor winding and RS (figure 1). When decay mode produces low ripple current for a given fixed off- the voltage across the sense resistor equals the DAC output volt- time (see figure 2). Low ripple current is desirable because the average current in the motor winding is more nearly equal to VBB I I PEAK TRIP SLOW (V ≥ 3.5 V) PFD MIXED (1.1 V ≤ V ≤ 3.1 V) PFD PFD FAST (V ≤ 0.8 V) PFD t OFF Dwg. WP-031-1 RS Drive Current (Normal) Recirculation (Fast Decay) Recirculation (Slow Decay)
Figure 1 — Load-Current Paths Figure 2 — Current Decay Waveforms
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