Datasheet LT8316 (Analog Devices) - 10

link to page 8 LT8316
OPERATION
As the load gets very light, the LT8316 reduces switching
CV/CC Regulation
frequency while maintaining the minimum current limit in Like a traditional voltage regulator, the LT8316 implements order to reduce current delivery while still properly sam- a G pling the output voltage. Because flyback pulses must be M transconductance amplifier that regulates the output voltage. In addition, the LT8316 includes a current generated to regulate the output, a minimum switching regulation loop which regulates the estimated output frequency of 3.5kHz is enforced. The minimum switch- current to a point set by the voltage on the IREG/SS pin. ing frequency determines how often the output voltage is Below the current setpoint, the output voltage is regulated sampled and introduces a minimum load requirement of for constant-voltage (CV) regulation. Below the voltage approximately 1% of the maximum load power. setpoint, the the output current is regulated for constant- Tying the SMODE pin to INTVCC enables Standby Mode, current (CC) regulation. which reduces the minimum switching frequency to 220Hz, reducing the minimum load requirement at the expense of a longer period between samples.
APPLICATIONS INFORMATION
The LT8316 is designed to be an easy-to-use, yet fully-
ENABLE and Undervoltage Lockout (UVLO)
featured flyback controller. With proper technique, it is A resistive divider from V simple to build an efficient and robust power solution. IN to the EN/UVLO pin imple- ments undervoltage lockout (UVLO). The EN/UVLO pin However, the voltage and power levels involved can be threshold is set at 1.22V. Upon startup, the EN/UVLO lethal.
Milliamperes from a high voltage power supply
pin exhibits a ~65mV hysteresis voltage to prevent
can cause heart fibrillation and death.
Never touch con- oscillations. ductive nodes while the circuit is active, and keep one The EN/UVLO pin can also be driven with logic levels and hand behind your back while probing. set by the output pin of a digital controller. Otherwise,
Depletion Startup FET
EN/UVLO can also be tied to BIAS or INTVCC to keep the chip enabled. The LT8316 features an internal depletion-mode FET, which has a negative threshold voltage and is therefore
Output Voltage
normally on. At startup, this FET charges the INTVCC The output voltage is programmed by the R capacitor to 12V so that the LT8316 has power to begin FB1 and RFB2 resistors depicted in the Block Diagram. The LT8316 switching. This removes the need for an external bleeder operates similarly to traditional current-mode switchers, resistor or other startup components. Once INTVCC is except in its use of a unique sample-and-hold error ampli- charged, the depletion-mode FET turns off. fier, which regulates the isolated output voltage from the The depletion FET is current-limited to avoid destructive sampled flyback pulse. power levels. To ensure start-up, do not load INTVCC or Operation is as follows: when the power switch M1 turns BIAS with excessive current while the chip is starting. off, the voltage across the tertiary winding rises. The amplitude of the flyback pulse is given as: VFLBK = (VOUT + VF + ISEC • ESR) • NTS, Rev. 0 10 For more information www.analog.com Document Outline Features Applications Typical Application Description Absolute Maximum Ratings Order Information Pin Configuration Electrical Characteristics Typical Performance Characteristics Pin Functions Block Diagram Operation Applications Information Package Description Typical Application Related Parts