Datasheet MA12040P (Infineon) - 3
| Fabricante | Infineon |
| Descripción | 2x40W ultra power efficient, fully integrated audio amplifier IC with I2S digital input |
| Páginas / Página | 88 / 3 — 3 Typical Application Block Diagram. Figure 3-1 Typical application block … |
| Revisión | 01_00 |
| Formato / tamaño de archivo | PDF / 1.8 Mb |
| Idioma del documento | Inglés |
3 Typical Application Block Diagram. Figure 3-1 Typical application block diagram. www.infineon.com
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3 Typical Application Block Diagram
100nF 1µF 1µF 1µF CFGD CGD0 CGD1 CFDC VDD VDD C P GDC N P 1µF D 0P N C D 0N 1P 1N C C AVDD G D D D FG G D G D FD DVDD CF C C G G VGD C C C CF C 1µF 1µF AVSS DVSS Analog power CREF C 1µF CDC DC 1µF PVDD and Charge pump power supplies 1µF CMSE reference PVDD voltages + 1µF 1µF PVSS 470µF Audio source Data pair 0 SD0 PVDD 0 DAC (0L,0R) r Power OUT0A I2S eve l amp CF0AP ro 10µF reci nt DAC iter CF0AN co PVSS CF0A e 0L SD1 m d lim PVDD 1 u an DAC r Vol Power OUT0B ion I2S amp cieve CF0BP rat 10µF re DAC CF0BN figu n PVSS CF0B SCK l co PVDD Power Clock and WS ne Clock management Power OUT1A timing CLK management han C amp CF1AP CLKM/S 10µF Temp sensor CF1AN PVSS CF1A 0R PVDD Control and protection Power OUT1B amp CF1BP 10µF E E R CF1BN BL O L0 L1 C EMC filter PVSS L A 0 1 UT F1B LIP SE SE D D depending on SC SD A A /M /ENA /C /ERR M M EPAD application Host system 5V
Figure 3-1 Typical application block diagram
Datasheet Please read the Important Notice and Warnings at the end of this document V 1.0
www.infineon.com
page 3 of 88 2018-07-17
100nF 1µF 1µF 1µF CFGD CGD0 CGD1 CFDC VDD VDD C P GDC N P 1µF D 0P N C D 0N 1P 1N C C AVDD G D D D FG G D G D FD DVDD CF C C G G VGD C C C CF C 1µF 1µF AVSS DVSS Analog power CREF C 1µF CDC DC 1µF PVDD and Charge pump power supplies 1µF CMSE reference PVDD voltages + 1µF 1µF PVSS 470µF Audio source Data pair 0 SD0 PVDD 0 DAC (0L,0R) r Power OUT0A I2S eve l amp CF0AP ro 10µF reci nt DAC iter CF0AN co PVSS CF0A e 0L SD1 m d lim PVDD 1 u an DAC r Vol Power OUT0B ion I2S amp cieve CF0BP rat 10µF re DAC CF0BN figu n PVSS CF0B SCK l co PVDD Power Clock and WS ne Clock management Power OUT1A timing CLK management han C amp CF1AP CLKM/S 10µF Temp sensor CF1AN PVSS CF1A 0R PVDD Control and protection Power OUT1B amp CF1BP 10µF E E R CF1BN BL O L0 L1 C EMC filter PVSS L A 0 1 UT F1B LIP SE SE D D depending on SC SD A A /M /ENA /C /ERR M M EPAD application Host system 5V
Figure 3-1 Typical application block diagram
Datasheet Please read the Important Notice and Warnings at the end of this document V 1.0
www.infineon.com
page 3 of 88 2018-07-17