Preliminary Datasheet CXT-STA4919 (Cissoid) - 7

CXT-STA4919 – Preliminary Datasheet Circuit Functionality Safe operating area, power dissipation, Functional Block diagram and PCB layout considerations:
The tiny PSOIC8 package with exposed
VIN VOUT
pad used for CXT-STA4919 requires ade- quate PCB layout in order to achieve effi-
OTP TSENSOR
cient thermal dissipation, the minimization of the junction operating temperature, and
OC CEB DETECT OCP VIN
maximizing the power dissipation taking
GND
advantage of the temperature behavior
0.9V VREF FB
capability of CXT-STA4919. The junction-to-air overall thermal re- sistance of CXT-STA4919 in PSOIC8 with exposed pad package relies, to a large extend, on the implementation of the cop- A PMOS transistor controls the level of per mounting pads that act as a heatsink current flowing from VIN to VOUT. An in- for the integrated circuit. The design must ternal voltage reference of 0.9V (highly take into consideration the size of the cop- stable over the whole temperature range) per pad and its placement on either of the provides the reference to which the volt- board surfaces, or both. age on the FB pin is compared. The inter- nal amplifier drives the gate of the PMOS The maximum power dissipation is deter- and regulates VOUT. mined by the maximum junction tempera- An on-chip temperature sensor with hyste- ture rating, the ambient temperature, and resis monitors the die temperature; if this junction-to-ambient thermal resistance: die temperature exceeds a predefined threshold, the PMOS transistor is disabled PDMAX =(TJMAX−TA)/RθJA and VOUT is connected to GND. In addition, an overcurrent protection cir- Where TJMAX=175°C and RθJA=RθJC+RθCA cuit is implemented which limits gracefully with RθJA55°C/W (depends on the size of the output current to a pre-defined value. the copper mounting pad and thermal coupling to the PSOIC8 package with ex- A Chip Enable function is provided thru the posed pad12). CEB pin: when tied low, the CXT- STA4919 is enabled and operates normal- Contact Cissoid for getting access to ref- ly; when CEB is tied high, CXT-STA4919 erence PCB layout information. is disabled. Note that the disable circuitry acts in the same way as the over- temperature disabling scheme as de- scribed above. 12 More information available soon. PUBLIC
1-May-19 Doc. PDS-181975 V1.0 WWW.CISSOID.COM
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