Datasheet AK7604 (Asahi Kasei Microdevices) - 6

[AK7604] ■ Pin Functions
No. Pin Name I/O
1 AINL2
I
2 AINR2
I
3 AINL3
I
4 AINR3
I
5 VCOM O 6
7 AVDD
VSS1 -8 VREFH -9 AOUT1L O 10 AOUT1R O 11 AOUT2L O 12 AOUT2R O 13 AOUT3L O 14 AOUT3R O 15 DZF
SDOUT2
RDY O
O
O 16 PDN I SDA I/O SO O SCL
SCLK
SI I
I
I CAD I CSN I TESTI I STO O SDOUT3
GPO O
O 17 18
19
20 21
22 Function
Power Supply
Lch Single-ended Input 2 Pin
AVDD
Rch Single-ended Input 2 Pin
AVDD
Lch Single-ended Input 3 Pin
AVDD
Rch Single-ended Input 3 Pin
AVDD
Analog Common Voltage Output Pin
Connect a 2.2µF ceramic capacitor between this pin and VSS1.
AVDD
This pin outputs “L” during power-down state. Do not connect
this pin to an external circuit.
Analog Power Supply Pin 3.0~3.6V (typ.3.3V)
Ground Pin, 0V
Analog High-level Reference Voltage Input Pin
AVDD
Connect this pin to AVDD.
DAC1 Lch Analog Output Pin
AVDD
This pin outputs “Hi-Z” during power-down state.
DAC1 Rch Analog Output Pin
AVDD
This pin outputs “Hi-Z” during power-down state.
DAC2 Lch Analog Output Pin
AVDD
This pin outputs “Hi-Z” during power-down state.
DAC2 Rch Analog Output Pin
AVDD
This pin outputs “Hi-Z” during power-down state.
DAC3 Lch Analog Output Pin
AVDD
This pin outputs “Hi-Z” during power-down state.
DAC3 Rch Analog Output Pin
AVDD
This pin outputs “Hi-Z” during power-down state.
Soft Defined Zero Detect Pin (GPO0 Output of DSP)
Serial Data Output 2 Pin
TVDD
RDY Signal Output Pin
Power-Down & Reset Pin
When “L”, the AK7604 is powered-down and the control
registers are reset to default state.
TVDD
The PDN pin should be “L” until all power supplies are ON, then
put the PDN pin to “H”.
Serial Data In/Output Pin for I2C I/F
TVDD
This pin outputs “Hi-Z” during power-down state.
Serial Data Output Pin for SPI I/F
This pin outputs “Hi-Z” during power-down state.
TVDD
This pin must be pulled up or pulled down.
Serial Data Clock Input Pin for I2C I/F
TVDD
Serial Data Clock Input Pin for SPI I/F
Serial Data Input Pin for SPI I/F
TVDD
I2C I/F Chip Address Pin
This pin must be pulled up or pulled down.
TVDD
SPI I/F Chip Select Pin
During power-down state or when SPI I/F is not in use, leave
this pin “H” level.
Test Input Pin
TVDD
It must be tied “L”.
Status Output Pin
This pin outputs “L” during power-down state.
TVDD
Serial Data Output 3 Pin
DSP GPO Output Pin (GPO1 Output of DSP) 018011601-E-00-PB 2018/09
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