Datasheet EFR32BG21 (Silicon Labs) - 6

link to page 6 link to page 3 link to page 3 EFR32BG21 Blue Gecko Wireless SoC Family Data Sheet System Overview
3. System Overview 3.1 Introduction
The EFR32 product family combines an energy-friendly MCU with a high performance radio transceiver. The devices are well suited for secure connected IoT multiprotocol devices requiring high performance and low energy consumption. This section gives a short intro- duction to the full radio and MCU system. The detailed functional description can be found in the EFR32xG21 Reference Manual. A block diagram of the EFR32BG21 family is shown in Figure 3.1 Detailed EFR32BG21 Block Diagram on page 6. The diagram shows a superset of features available on the family, which vary by OPN. For more information about specific device features, consult Ordering Information.
Radio Transciever Port I/O Configuration
IOVDD
RF Frontend DEMOD
I
LNA Digital Peripherals FRC
Q
PGA IFADC BUFC
RF2G4_IO1
LETIMER PA Port A
RF2G4_IO2 PAn
AGC Drivers Frequency PA TIMER Synthesizer CRC RAC MOD RTC Port B
PBn
Drivers USART Reset Port
RESETn
Management ARM Cortex-M33 Core I2C Mapper Port C
PCn
Drivers Unit Serial Wire Up to 1024 kB Flash
Debug Signals
and ETM Brown Out / Program Memory Security
(shared w/GPIO)
Debug / Power-On Acceleration Port D
PDn
Up to 96 KB RAM Drivers Programming Reset A A TRNG Trust Zone H P B B Energy Management Floating Point Unit CRC
PAVDD
DMA Controller
RFVDD IOVDD
Analog Peripherals
AVDD
Watchdog Timer Internal
DVDD
Reference Clock Management Voltage VDD ULFRCO Regulator 12-bit ADC FSRCO
DECOUPLE
HFRCOEM2 Input Mux Port Mapper LFRCO
LFXTAL_I
LFXO
+ LFXTAL_O -
HFRCO
HFXTAL_I
Analog Comparator HFXO
HFXTAL_O
Figure 3.1. Detailed EFR32BG21 Block Diagram 3.2 Radio
The EFR32BG21 Blue Gecko features a highly configurable radio transceiver supporting the Bluetooth Low Energy wireless protocol.
3.2.1 Antenna Interface
The 2.4 GHz antenna interface consists of two single-ended pins (RF2G4_IO1 and RF2G4_IO2) that interface directly to two LNAs and two 10 dBm PAs. For devices that support 20 dBm, these pins also interface to the 20 dBm on-chip balun. Integrated switches select either RF2G4_IO1 or RF2G4_IO2 to be the active path. The external components and power supply connections for the antenna interface typical applications are shown in the RF Matching Networks section.
silabs.com
| Building a more connected world. Rev. 1.0 | 6 Document Outline 1. Feature List 2. Ordering Information 3. System Overview 3.1 Introduction 3.2 Radio 3.2.1 Antenna Interface 3.2.2 Fractional-N Frequency Synthesizer 3.2.3 Receiver Architecture 3.2.4 Transmitter Architecture 3.2.5 Packet and State Trace 3.2.6 Data Buffering 3.2.7 Radio Controller (RAC) 3.3 General Purpose Input/Output (GPIO) 3.4 Clocking 3.4.1 Clock Management Unit (CMU) 3.4.2 Internal and External Oscillators 3.5 Counters/Timers and PWM 3.5.1 Timer/Counter (TIMER) 3.5.2 Low Energy Timer (LETIMER) 3.5.3 Real Time Clock with Capture (RTCC) 3.5.4 Back-Up Real Time Counter 3.5.5 Watchdog Timer (WDOG) 3.6 Communications and Other Digital Peripherals 3.6.1 Universal Synchronous/Asynchronous Receiver/Transmitter (USART) 3.6.2 Inter-Integrated Circuit Interface (I2C) 3.6.3 Peripheral Reflex System (PRS) 3.7 Security Features 3.7.1 Standard Security 3.7.2 True Random Number Generator 3.8 Analog 3.8.1 Analog Comparator (ACMP) 3.8.2 Analog to Digital Converter (ADC) 3.9 Reset Management Unit (RMU) 3.10 Core and Memory 3.10.1 Processor Core 3.10.2 Memory System Controller (MSC) 3.10.3 Linked Direct Memory Access Controller (LDMA) 3.11 Memory Map 3.12 Configuration Summary 4. Electrical Specifications 4.1 Electrical Characteristics 4.1.1 Absolute Maximum Ratings 4.1.2 General Operating Conditions 4.1.3 Thermal Characteristics 4.1.4 Current Consumption 4.1.4.1 MCU current consumption at 1.8V 4.1.4.2 MCU current consumption at 3.0V 4.1.4.3 Radio current consumption at 1.8V 4.1.4.4 Radio current consumption at 3.0V 4.1.5 2.4 GHz RF Transceiver Characteristics 4.1.5.1 RF Transmitter Characteristics 4.1.5.2 RF Receiver Characteristics 4.1.6 Flash Characteristics 4.1.7 Wake Up, Entry, and Exit times 4.1.8 Oscillators 4.1.8.1 High Frequency Crystal Oscillator 4.1.8.2 Low Frequency Crystal Oscillator 4.1.8.3 High Frequency RC Oscillator (HFRCO) 4.1.8.4 Fast Start_Up RC Oscillator (FSRCO) 4.1.8.5 Low Frequency RC Oscillator 4.1.8.6 Ultra Low Frequency RC Oscillator 4.1.9 GPIO Pins (3V GPIO pins) 4.1.10 Analog to Digital Converter (ADC) 4.1.11 Analog Comparator (ACMP) 4.1.12 Temperature Sense 4.1.13 Brown Out Detectors 4.1.13.1 DVDD BOD 4.1.13.2 LE DVDD BOD 4.1.13.3 AVDD and VIO BODs 4.1.14 SPI Electrical Specifications 4.1.14.1 SPI Master Timing 4.1.14.2 SPI Slave Timing 4.1.15 I2C Electrical Specifications 4.1.15.1 I2C Standard-mode (Sm) 4.1.15.2 I2C Fast-mode (Fm) 4.1.15.3 I2C Fast-mode Plus (Fm+) 4.2 Typical Performance Curves 4.2.1 Supply Current 4.2.2 2.4 GHz Radio 5. Typical Connection Diagrams 5.1 Power 5.2 RF Matching Networks 5.2.1 2.4 GHz 0 dBm Matching Network 5.2.2 2.4 GHz 10 dBm Matching Network 5.2.3 2.4 GHz 20 dBm Matching Network 5.3 Other Connections 6. Pin Definitions 6.1 QFN32 2.4GHz Device Pinout 6.2 Alternate Function Table 6.3 Analog Peripheral Connectivity 6.4 Digital Peripheral Connectivity 7. QFN32 Package Specifications 7.1 QFN32 Package Dimensions 7.2 QFN32 PCB Land Pattern 7.3 QFN32 Package Marking 8. Revision History