Datasheet TMC6200 (TRINAMIC) - 8

TMC6200 DATASHEET (Rev. 1.03 / 2019-FEB-13) 8
Pin TQFP Type Function
LSU 5 Low side gate driver output. Output of internal 11.5V gate voltage regulator and supply pin of low side gate drivers. Attach 2.2µF to 22µF ceramic capacitor to GND plane near to pin for best performance. Use 12VOUT 6 at least 5-10 times more capacity than for bootstrap capacitors. In case an external gate voltage supply is available, tie VSA and 12VOUT to the external supply. Output of internal 5V regulator. Attach 2.2µF to 10µF ceramic 5VOUT 7 capacitor to GNDA near to pin for best performance. GNDA 8 Analog GND. Connect to GND plane near pin. CURU 9 AO Output of current sense amplifier. CURV 10 AO Output of current sense amplifier. CURW 11 AO Output of current sense amplifier. Center reference for current sense amplifiers (leave open for VOFS/TEST 12 AI 5VOUT/3 offset voltage). SPI chip select input (negative active) (SPE=1) or CSN_IDRV0 13 DI Configuration input for gate driver current LSB (SPE=0) SPI serial clock input (SPE=1) or SCK_IDRV1 14 DI Configuration input for gate driver current MSB (SPE=0) SPI data input (SPE=1) or SDI_AMPLx10 15 DI Configuration input for current sense amplifier 5x or 10x amplification (SPE=0) SPI data output (tristate) (SPE=1) or SDO_SINGLE 16 DIO Configuration input for internal bridge control mode (0: dual line, 1: xH=phase polarity, xL=phase enable) (SPE=0) DI High side control input (or bridge polarity in single mode) UH 17 (pd) DI Low side control input (or bridge enable in single mode) UL 18 (pd) VCC_IO 19 3.3V to 5V IO supply voltage for all digital pins. DI High side control input (or bridge polarity in single mode) VH 20 (pd) DI Low side control input (or bridge enable in single mode) VL 21 (pd) DI High side control input (or bridge polarity in single mode) WH 22 (pd) DI Low side control input (or bridge enable in single mode) WL 23 (pd) CLK input. Tie to GND using short wire for internal clock or CLK 24 DI supply external clock. Internal clock-fail over circuit protects against loss of external clock signal. Mode selection input. When tied low, the chip is in standalone DI mode and SPI pins have their configuration pin functions. SPE 25 (pd) When tied high, the SPI interface is enabled. Integrated pull down resistor. Diagnostics output. FAULT 26 DO High upon driver error condition. Clear by cycling EN. Positive active enable input. The power stage becomes DRV_EN 27 DI switched off (all motor outputs floating) when this pin becomes driven to a low level. Cycle low to clear FAULT. Analog supply voltage for 11.5V and 5V regulator. Normally VSA 29 tied to VS. Provide a 100nF filtering capacitor to GND. CPO 30 Charge pump capacitor output. www.trinamic.com