Datasheet TDC-GPX2 (AustriaMicroSystems) - 3

TDC-GPX2 −
General Description
Block Diagram
The functional blocks of this device are shown below:
Figure 3: Functional Blocks of TDC-GPX2
3 8 8 8 3 8 3 1 1 1 3 1 D D D D DD DD DD DD TV TV CV DV DV DV DISABLEP LCLKINP DISABLEN LCLKINN SDO1P STOP1P
Encoder
SDO1N
TDC Serializer
STOP1N FRAME1P
44:1 ... 14:1 FIFO
FRAME1N SDO3P
Encoder
STOP3P SDO3N
TDC Serializer
STOP3N FRAME3P
44:1 ... 14:1 FIFO
FRAME3N SDO2P
Encoder
STOP2P SDO2N
TDC Serializer
STOP2N FRAME2P
44:1 ... 14:1 FIFO
FRAME2N SDO4P
Encoder
STOP4P SDO4N
TDC Serializer
STOP4N FRAME4P
44:1 ... 14:1 FIFO
FRAME4N
Reference
RSTIDXP LCLKOUTP
Clock
LCLKOUTN RSTIDXN
Index Counter
CVDD18O
Encoder Configuration
REFCLKP
LVR
TVDD18O
TDC Serial Interface
REFCLKN DVDD18O I 3 T O K I O Y C 3 C 3 P S S 3 S IT S SSN SC O DD MO MI DD F O F RRU PAR DV E RV RE T RE IN
ams Datasheet Page 3
[v1-03] 2017-Dec-18 Document Feedback Document Outline General Description Key Benefits & Features Applications Block Diagram Pin Assignments Pin Diagram Pin Description Absolute Maximum Ratings Recommended Operation Conditions Converter Characteristics Power Supply Characteristic Reference Clock and Stop Input Requirements LVDS Data Interface Characteristics Serial Communication Interface Typical Operating Characteristics Histograms Integral Non-Linearity Register Description Configuration Register Overview Detailed Configuration Register Description Read Register Overview Detailed Description Time Measurements and Results Measurements of TDC-GPX2 Output Results Calculation of Time Differences Resolution RMS-Resolution Versus Effective Resolution High Resolution Combining Two Stop Channels Channel Combination for Low Pulse-to-Pulse Spacing Channel Combination for Pulse Width Measurement Input Pins for Time Measurement REFCLKP/N: Reference Clock Input REFOSCI/O: Quartz Driver as Reference Clock RSTIDXP/N: Reference Index Counter Reset STOP1…STOP4P/N: Stop Channels DISABLE/N: Stop Disable Input Levels, CMOS or LVDS LVDS Output Interface Digital Output Interface Output Setup and Configuration: LVDS Output Buffers Differential LCLKIN Input LVDS Single Data Read Output Interface (SDR) LVDS Double Data Read Output Interface (DDR) LVDS Output Test Pattern SPI Communication Interface General Detailed Pin Description Communication Commands (Opcodes) Detailed Command Description Initialization Reset Write / Incremental Write Read / Incremental Read Using SPI Interface for Read-Out of Stop Results Coding of Results Configuration of LSB by REFCLK_DIVISIONS Examples for Codes of Time Measurements Results Maximum Time Differences Conversion Latency and Conversion Rate Converter Latency LVDS Synchronization Latency Conversion Rate Peak Conversion Rate Read-Out Rate Average Conversion Rate Examples for Read-Out Rate with LVDS FIFOs for Adapting Peak and Average Conversion Rate Application Information Configuration Examples Typical Configuration for LVDS Example C++ Code Schematic External Components PCB Layout Package Drawings & Markings Mechanical Data QFN64 QFN64 Tray Information QFP64 QFP64 Tape & Reel Information Soldering & Storage Information Ordering & Contact Information RoHS Compliant & ams Green Statement Copyrights & Disclaimer Document Status Revision Information Content Guide