Datasheet AS6500 (AustriaMicroSystems) - 3
| Fabricante | AustriaMicroSystems |
| Descripción | Time-to-Digital Converter 4-channel TDC with CMOS inputs |
| Páginas / Página | 56 / 3 — General Description. Figure 1: Added Value of Using AS6500. Benefits. … |
| Revisión | 3-00 |
| Formato / tamaño de archivo | PDF / 1.9 Mb |
| Idioma del documento | Inglés |
General Description. Figure 1: Added Value of Using AS6500. Benefits. Features
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1 General Description
The AS6500 is a high performance time-to-digital converter (TDC) frontend device. It is a derivative of TDC-GPX2, with CMOS inputs and serial SPI output only. It comes in a QFN40 package. AS6500 achieves high measurement performance and high data throughput. High configuration flexibility and unlimited measurement range cover many applications, ranging from portable handheld laser range equipment to ambitious time-of-flight measurements of high performance. AS6500 calculates calibrated stop measurements, referenced to the applied reference clock. Combinations of single shot accuracy of 10ps with lowest pulse-to-pulse spacing <10ns and maximum data input burst rate of 70 MSPS per stop input are possible. Total data throughput via SPI is about 1.5 MSPS. 1.1 Key Benefits & Features The benefits and features of AS6500, 4-Channel Time-to-Digital Converter, are listed below:
Figure 1: Added Value of Using AS6500 Benefits Features
● 4 stop channels with 20 ns pulse-to-pulse spacing ● 2 combined channels with 10 ns pulse-to- pulse spacing ● Simple data post-processing thanks to ● Maximum 1.5 MSPS via SPI calibrated results ● Single shot accuracy 20 ps RMS resolution per channel, 10 ps RMS with high resolution option ● Unlimited measuring range 0 s to 16 s ● Differential reference clock input 2 MHz to 12.5 MHz ● Event assignment thanks to reference clock ● Inputs CMOS level index simplifies coincidence measurements ● ● Readout with SPI, used also for configuration Easy pulse width measurements ● ● 16-stage FIFO per channel High efficiency thanks high sample rate ● Automatic calibration to reference clock (no PLL or DLL) ● Compact design thanks to small package ● Supply voltage 3.3 V and low number of external components ● Power dissipation 60 mW ● Reduced cooling thanks to low power ● Standby current 60 µA consumption ● QFN40 package (6 mm x 6 mm) Datasheet • PUBLIC DS000640 • v3-00 • 2019-Feb-21 56 │ 3 Document Outline Content Guide 1 General Description 1.1 Key Benefits & Features 1.2 Applications 1.3 Block Diagram 2 Ordering Information 3 Pin Assignment 3.1 Pin Diagram 3.2 Pin Description 4 Absolute Maximum Ratings 5 Recommended Operation Conditions 6 Typical Characteristics 6.1 Converter Characteristics 6.2 Power Supply Characteristics 6.3 Reference Clock and Stop Input Requirements 6.4 Serial Communication Interface 6.5 Typical Operating Characteristics 7 Register Description 7.1 Register Overview 7.2 Detailed Register Description 7.2.1 CFG0 Register (Address 0) 7.2.2 CFG1 Register (Address 1) 7.2.3 CFG2 Register (Address 2) 7.2.4 CFG3, CFG4, CFG5 Registers (Addresses 3 to 5) 7.2.5 CFG6 Register (Address 6) 7.2.6 CFG7 Register (Address 7) 7.2.7 CFG8 to CFG15 Register (Addresses 8 to 15) 7.2.8 CFG16 Register (Address 16) 7.2.9 CHANNEL1 Result Register (Addresses 8 to 13) 7.2.10 CHANNEL2 Result Register (Addresses 14 to 19) 7.2.11 CHANNEL3 Result Register (Addresses 20 to 25) 7.2.12 CHANNEL4 Result Register (Addresses 26 to 31) 8 Detailed Description 8.1 Time Measurements and Results 8.1.1 Measurements of AS6500 8.1.2 Output Results 8.1.3 Calculation of Time Differences GENERAL APPROACH 8.2 Resolution 8.2.1 RMS-Resolution versus Effective Resolution 8.2.2 High Resolution 8.3 Combining Two Stop Channels 8.3.1 Channel Combination for Low Pulse-to-Pulse Spacing 8.3.2 Channel Combination for Pulse Width Measurement 8.4 Input Pins for Time Measurement 8.4.1 REFCLK: Reference Clock Input 8.4.2 RSTIDX: Reference Index Counter Reset 8.4.3 STOP1 to STOP4: Stop Channels 8.4.4 DISABLE: Stop Disable SOFTWARE ENABLE (HIT_ENA_STOP1…4) PIN ENABLE (PIN_ENA_XXX) 8.5 SPI Communication Interface 8.5.1 General 8.5.2 Detailed Pin Description 8.5.3 Communication Commands (Opcodes) 8.5.4 Data Readout via SPI Interface 8.6 Coding of Results 8.6.1 Configuration of LSB by REFCLK_DIVISIONS 8.6.2 Examples for Codes of Time Measurements Results 8.6.3 Maximum Time Differences 8.7 Conversion Latency and Conversion Rate Converter Latency 8.8 Conversion Rate 8.8.1 Peak Conversion Rate 8.8.2 Read-Out Rate 8.8.3 Average Conversion Rate 8.8.4 FIFOs for Adapting Peak and Average Conversion Rate 9 Application Information 9.1 Configuration Examples 9.2 Example C++ Code 9.3 Schematic 9.4 External Components 10 Package Drawings & Markings 11 Reel Information 12 Soldering & Storage Information 13 Revision Information 14 Legal Information
1 General Description
The AS6500 is a high performance time-to-digital converter (TDC) frontend device. It is a derivative of TDC-GPX2, with CMOS inputs and serial SPI output only. It comes in a QFN40 package. AS6500 achieves high measurement performance and high data throughput. High configuration flexibility and unlimited measurement range cover many applications, ranging from portable handheld laser range equipment to ambitious time-of-flight measurements of high performance. AS6500 calculates calibrated stop measurements, referenced to the applied reference clock. Combinations of single shot accuracy of 10ps with lowest pulse-to-pulse spacing <10ns and maximum data input burst rate of 70 MSPS per stop input are possible. Total data throughput via SPI is about 1.5 MSPS. 1.1 Key Benefits & Features The benefits and features of AS6500, 4-Channel Time-to-Digital Converter, are listed below:
Figure 1: Added Value of Using AS6500 Benefits Features
● 4 stop channels with 20 ns pulse-to-pulse spacing ● 2 combined channels with 10 ns pulse-to- pulse spacing ● Simple data post-processing thanks to ● Maximum 1.5 MSPS via SPI calibrated results ● Single shot accuracy 20 ps RMS resolution per channel, 10 ps RMS with high resolution option ● Unlimited measuring range 0 s to 16 s ● Differential reference clock input 2 MHz to 12.5 MHz ● Event assignment thanks to reference clock ● Inputs CMOS level index simplifies coincidence measurements ● ● Readout with SPI, used also for configuration Easy pulse width measurements ● ● 16-stage FIFO per channel High efficiency thanks high sample rate ● Automatic calibration to reference clock (no PLL or DLL) ● Compact design thanks to small package ● Supply voltage 3.3 V and low number of external components ● Power dissipation 60 mW ● Reduced cooling thanks to low power ● Standby current 60 µA consumption ● QFN40 package (6 mm x 6 mm) Datasheet • PUBLIC DS000640 • v3-00 • 2019-Feb-21 56 │ 3 Document Outline Content Guide 1 General Description 1.1 Key Benefits & Features 1.2 Applications 1.3 Block Diagram 2 Ordering Information 3 Pin Assignment 3.1 Pin Diagram 3.2 Pin Description 4 Absolute Maximum Ratings 5 Recommended Operation Conditions 6 Typical Characteristics 6.1 Converter Characteristics 6.2 Power Supply Characteristics 6.3 Reference Clock and Stop Input Requirements 6.4 Serial Communication Interface 6.5 Typical Operating Characteristics 7 Register Description 7.1 Register Overview 7.2 Detailed Register Description 7.2.1 CFG0 Register (Address 0) 7.2.2 CFG1 Register (Address 1) 7.2.3 CFG2 Register (Address 2) 7.2.4 CFG3, CFG4, CFG5 Registers (Addresses 3 to 5) 7.2.5 CFG6 Register (Address 6) 7.2.6 CFG7 Register (Address 7) 7.2.7 CFG8 to CFG15 Register (Addresses 8 to 15) 7.2.8 CFG16 Register (Address 16) 7.2.9 CHANNEL1 Result Register (Addresses 8 to 13) 7.2.10 CHANNEL2 Result Register (Addresses 14 to 19) 7.2.11 CHANNEL3 Result Register (Addresses 20 to 25) 7.2.12 CHANNEL4 Result Register (Addresses 26 to 31) 8 Detailed Description 8.1 Time Measurements and Results 8.1.1 Measurements of AS6500 8.1.2 Output Results 8.1.3 Calculation of Time Differences GENERAL APPROACH 8.2 Resolution 8.2.1 RMS-Resolution versus Effective Resolution 8.2.2 High Resolution 8.3 Combining Two Stop Channels 8.3.1 Channel Combination for Low Pulse-to-Pulse Spacing 8.3.2 Channel Combination for Pulse Width Measurement 8.4 Input Pins for Time Measurement 8.4.1 REFCLK: Reference Clock Input 8.4.2 RSTIDX: Reference Index Counter Reset 8.4.3 STOP1 to STOP4: Stop Channels 8.4.4 DISABLE: Stop Disable SOFTWARE ENABLE (HIT_ENA_STOP1…4) PIN ENABLE (PIN_ENA_XXX) 8.5 SPI Communication Interface 8.5.1 General 8.5.2 Detailed Pin Description 8.5.3 Communication Commands (Opcodes) 8.5.4 Data Readout via SPI Interface 8.6 Coding of Results 8.6.1 Configuration of LSB by REFCLK_DIVISIONS 8.6.2 Examples for Codes of Time Measurements Results 8.6.3 Maximum Time Differences 8.7 Conversion Latency and Conversion Rate Converter Latency 8.8 Conversion Rate 8.8.1 Peak Conversion Rate 8.8.2 Read-Out Rate 8.8.3 Average Conversion Rate 8.8.4 FIFOs for Adapting Peak and Average Conversion Rate 9 Application Information 9.1 Configuration Examples 9.2 Example C++ Code 9.3 Schematic 9.4 External Components 10 Package Drawings & Markings 11 Reel Information 12 Soldering & Storage Information 13 Revision Information 14 Legal Information