Datasheet Si8935/36/37 (Silicon Labs) - 5
| Fabricante | Silicon Labs |
| Descripción | Delta-Sigma Modulator for Voltage Measurement |
| Páginas / Página | 25 / 5 — 2.1 Modulator. Figure 2.2. Typical 2nd Order Delta-Sigma Modulator Block … |
| Revisión | 0.1 |
| Formato / tamaño de archivo | PDF / 471 Kb |
| Idioma del documento | Inglés |
2.1 Modulator. Figure 2.2. Typical 2nd Order Delta-Sigma Modulator Block Diagram. Table 2.1. Modulator Output
Línea de modelo para esta hoja de datos
Versión de texto del documento
Si8935/36/37 Data Sheet System Overview
2.1 Modulator
The output of the Si8935/36/37 comes from a second-order, delta-sigma modulator like that shown in the figure below. The modulator provides 1-bit datastream whose average represents the input analog voltage. 0 V across the inputs is represented at the output by a pulse train that has 50% ones density. Specified full-scale at the input (e.g., +2.25 V) produces an output datastream that has 92.87% ones density. Ʃ ʃ Ʃ ʃ ʃ REF 1-Bit DAC
Figure 2.2. Typical 2nd Order Delta-Sigma Modulator Block Diagram Table 2.1. Modulator Output Single-Ended Input Bitstream % Ones
2.25 V 92.87% 1.125 V 71.44% 0 V 50%
silabs.com
| Building a more connected world. Preliminary Rev. 0.1 | 5 Document Outline 1. Ordering Guide 2. System Overview 2.1 Modulator 3. Voltage Sense Application 4. Electrical Specifications 4.1 Regulatory Information 5. Pin Descriptions 5.1 Si8935/36/37 Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Document Revision History
2.1 Modulator
The output of the Si8935/36/37 comes from a second-order, delta-sigma modulator like that shown in the figure below. The modulator provides 1-bit datastream whose average represents the input analog voltage. 0 V across the inputs is represented at the output by a pulse train that has 50% ones density. Specified full-scale at the input (e.g., +2.25 V) produces an output datastream that has 92.87% ones density. Ʃ ʃ Ʃ ʃ ʃ REF 1-Bit DAC
Figure 2.2. Typical 2nd Order Delta-Sigma Modulator Block Diagram Table 2.1. Modulator Output Single-Ended Input Bitstream % Ones
2.25 V 92.87% 1.125 V 71.44% 0 V 50%
silabs.com
| Building a more connected world. Preliminary Rev. 0.1 | 5 Document Outline 1. Ordering Guide 2. System Overview 2.1 Modulator 3. Voltage Sense Application 4. Electrical Specifications 4.1 Regulatory Information 5. Pin Descriptions 5.1 Si8935/36/37 Pin Descriptions 6. Packaging 6.1 Package Outline: 8-Pin Wide Body Stretched SOIC 6.2 Package Outline: 8-Pin Narrow Body SOIC 6.3 Land Pattern: 8-Pin Wide Body Stretched SOIC 6.4 Land Pattern: 8-Pin Narrow Body SOIC 6.5 Top Marking: 8-Pin Wide Body Stretched SOIC 6.6 Top Marking: 8-Pin Narrow Body SOIC 7. Document Revision History