Datasheet ADSP-21261, ADSP-21262, ADSP-21266 (Analog Devices) - 5

ADSP-21261 /ADSP-21262 /ADSP-21266
The ADSP-2126x’s SRAM can be configured as a maximum of
DMA Controller
64K words of 32-bit data, 128K words of 16-bit data, 42K words The ADSP-2126x’s on-chip DMA controller allows zero-over- of 48-bit instructions (or 40-bit data), or combinations of differ- head data transfers without processor intervention. The DMA ent word sizes up to two megabits. All of the memory can be controller operates independently and invisibly to the processor accessed as 16-bit, 32-bit, 48-bit, or 64-bit words. A 16-bit float- core, allowing DMA operations to occur while the core is simul- ing-point storage format is supported that effectively doubles taneously executing its program instructions. DMA transfers the amount of data that can be stored on-chip. Conversion can occur between the ADSP-2126x’s internal memory and its between the 32-bit floating-point and 16-bit floating-point for- serial ports, the SPI-compatible (serial peripheral interface) mats is performed in a single instruction. While each memory port, the IDP (input data port), parallel data acquisition port block can store combinations of code and data, accesses are (PDAP), or the parallel port. Up to 22 channels of DMA are most efficient when one block stores data using the DM bus for available on the ADSP-2126x—one for the SPI interface, 12 via transfers, and the other block stores instructions and data using the serial ports, eight via the input data port, and one via the the PM bus for transfers. processor’s parallel port. Programs can be downloaded to the Using the DM bus and PM buses, with one dedicated to each ADSP-2126x using DMA transfers. Other DMA features memory block, assures single-cycle execution with two data include interrupt generation upon completion of DMA trans- transfers. In this case, the instruction must be available in the fers, and DMA chaining for automatic linked DMA transfers. cache.
Table 4. Internal Memory Space (ADSP-21261) IOP Registers 0x0000 0000–0003 FFFF Extended Precision Normal or Long Word (64 Bits) Instruction Word (48 Bits) Normal Word (32 Bits) Short Word (16 Bits)
Block 0 SRAM Block 0 SRAM Block 0 SRAM Block 0 SRAM 0x0004 0000–0x0004 1FFF 0x0008 0000–0x0008 2AAA 0x0008 0000–0x0008 3FFF 0x0010 0000–0x0010 7FFF Reserved Reserved Reserved Reserved 0x0004 2000–0x0005 7FFF 0x0008 4000–0x000A FFFF 0x0010 8000–0x0015 FFFF Block 0 ROM Block 0 ROM Block 0 ROM Block 0 ROM 0x0005 8000–0x0005 DFFF 0x000A 0000–0x000A 7FFF 0x000B 0000–0x000B BFFF 0x0016 0000–0x0017 7FFF Reserved Reserved Reserved Reserved 0x0005 E000–0x0005 FFFF 0x000B C000–0x000B FFFF 0x0017 8FFF–0x0017 FFFF Block 1 SRAM Block 1 SRAM Block 1 SRAM Block 1 SRAM 0x0006 0000–0x0006 1FFF 0x000C 0000–0x000C 2AAA 0x000C 0000–0x000C 3FFF 0x0018 0000–0x0018 7FFF Reserved Reserved Reserved Reserved 0x0006 2000–0x0007 7FFF 0x000C 4000–0x000E FFFF 0x0018 8000–0x001D FFFF Block 1 ROM Block 1 ROM Block 1 ROM Block 1 ROM 0x0007 8000–0x0007 DFFF 0x000E 0000–0x000E 7FFF 0x000F 0000–0x000F BFFF 0x001E 0000–0x001F 7FFF Reserved Reserved Reserved Reserved 0x0007 E000–0x0007 FFFF 0x000F C000–0x000F FFFF 0x0000 Rev. G | Page 5 of 48 | December 2012 Document Outline Summary Table of Contents Revision History General Description Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Memory and I/O Interface Features Dual-Ported On-Chip Memory DMA Controller Digital Application Interface (DAI) Serial Ports Serial Peripheral (Compatible) Interface Parallel Port Timers ROM-Based Security Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Address Data Pins as Flags Boot Modes Core Instruction Rate to CLKIN Ratio Modes Address Data Modes Product Specifications Operating Conditions Electrical Characteristics Package Information ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing DAI Pin-to-Pin Direct Routing Precision Clock Generator (Direct Pin Routing) Flags Memory Read—Parallel Port Memory Write—Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) SPI Interface Protocol—Master SPI Interface Protocol—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Environmental Conditions Thermal Characteristics 144-Lead LQFP Pin Configurations 136-Ball BGA Pin Configurations Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide