Datasheet ADSP-21362, ADSP-21363, ADSP-21364, ADSP-21365, ADSP-21366 (Analog Devices) - 7

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ADSP-21362/ADSP-21363/ADSP-2 1364/ADSP-21365/ADSP-21366
generate either center-aligned or edge-aligned PWM wave- Serial ports operate in four modes: forms. In addition, it can generate complementary signals on • Standard DSP serial mode two outputs in paired mode or independent signals in non- paired mode (applicable to a single group of four PWM • Multichanne l (TDM) mode waveforms). • I2S mode The PWM generator is capable of operating in two distinct • Left-justified sample pair mode modes while generating center-aligned PWM waveforms: single update mode or double update mode. In single update mode,
S/PDIF-Compatible Digital Audio Receiver/Transmitter
the duty cycle values are programmable only once per PWM The S/PDIF transmitter has no separate DMA channels. It period. This results in PWM patterns that are symmetrical receives audio data in serial format and converts it into a about the midpoint of the PWM period. In double update biphase encoded signal. The serial data input to the transmitter mode, a second updating of the PWM registers is implemented can be formatted as left-justified, I2S, or right-justified with at the midpoint of the PWM period. In this mode, it is possible word widths of 16, 18, 20, or 24 bits. to produce asymmetrical PWM patterns that produce lower The serial data, clock, and frame sync inputs to the S/PDIF harmonic distortion in 3-phase PWM inverters. transmitter are routed through the signal routing unit (SRU).
Digital Audio Interface (DAI)
They can come from a variety of sources such as the SPORTs, external pins, the precision clock generators (PCGs), or the The digital audio interface (DAI) provides the ability to connect sample rate converters (SRC) and are controlled by the SRU various peripherals to any of the DSP’s DAI pins (DAI_P20–1). control registers. Programs make these connections using the signal routing unit (SRU, shown in Figure 1).
Digital Transmission Content Protection (DTCP)
The SRU is a matrix routing unit (or group of multiplexers) that The DTCP specification defines a cryptographic protocol for enables the peripherals provided by the DAI to be intercon- protecting audio entertainment content from illegal copying, nected under software control. This allows easy use of the intercepting, and tampering as it traverses high performance DAI-associated peripherals for a wider variety of applications by digital buses, such as the IEEE 1394 standard. Only legitimate using a larger set of algorithms than is possible with nonconfig- entertainment content delivered to a source device via another urable signal paths. approved copy protection system (such as the DVD content The DAI includes six serial ports, an S/PDIF receiver/transmit- scrambling system) is protected by this copy protection system. ter, a DTCP cipher, a precision clock generator (PCG), eight This feature is available on the ADSP-21362 and channels of asynchronous sample rate converters, an input data ADSP-21365 processors only. Licensing through DTLA is port (IDP), an SPI port, six flag outputs and six flag inputs, and required for these products. Visit www.dtcp.com for more three timers. The IDP provides an additional input path to the information. ADSP-2136x core, configurable as either eight channels of I2S
Memory-to-Memory (MTM)
serial data or as seven channels plus a single 20-bit wide syn- chronous parallel data acquisition port. Each data channel has If the DTCP module is not used, the memory-to-memory DMA its own DMA channel that is independent from the processor’s module allows internal memory copies for a standard DMA. serial ports.
Synchronous/Asynchronous Sample Rate Converter (SRC) Serial Ports
The sample rate converter (SRC) contains four SRC blocks and The processor features six synchronous serial ports that provide is the same core as that used in the AD1896 192 kHz stereo an inexpensive interface to a wide variety of digital and mixed- asynchronous sample rate converter and provides up to 140 dB signal peripheral devices such as Analog Devices’ AD183x fam- SNR. The SRC block is used to perform synchronous or ily of audio codecs, ADCs, and DACs. The serial ports are made asynchronous sample rate conversion across independent stereo up of two data lines, a clock, and a frame sync and they can channels, without using internal processor resources. The four operate at maximum f SRC blocks can also be configured to operate together to con- PCLK/4. The data lines can be pro- grammed to either transmit or receive and each data line has a vert multichannel audio data without phase mismatches. dedicated DMA channel. Finally, the SRC is used to clean up audio data from jittery clock sources such as the S/PDIF receiver. Serial ports are enabled via 12 programmable and simultaneous receive or transmit pins that support up to 24 transmit or 24 The S/PDIF and SRC are not available on the ADSP-21363 receive channels of audio data when all six SPORTs are enabled, models. or six full duplex TDM streams of 128 channels per frame.
Input Data Port (IDP)
Serial port data can be automatically transferred to and from The IDP provides up to eight serial input channels—each with on-chip memory via dedicated DMA channels. Each of the its own clock, frame sync, and data inputs. The eight channels serial ports can work in conjunction with another serial port to are automatically multiplexed into a single 32-bit by eight-deep provide TDM support. One SPORT provides two transmit sig- FIFO. Data is always formatted as a 64-bit frame and divided nals while the other SPORT provides the two receive signals. into two 32-bit words. The serial protocol is designed to receive The frame sync and clock are shared. Rev. J | Page 7 of 60 | July 2013 Document Outline Summary Dedicated Audio Components Table of Contents Revision History General Description SHARC Family Core Architecture SIMD Computational Engine Independent, Parallel Computation Units Data Register File Context Switch Universal Registers Timer Single-Cycle Fetch of Instruction and Four Operands Instruction Cache Data Address Generators with Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set On-Chip Memory On-Chip Memory Bandwidth ROM-Based Security Family Peripheral Architecture Parallel Port Serial Peripheral (Compatible) Interface Pulse-Width Modulation Digital Audio Interface (DAI) Serial Ports S/PDIF-Compatible Digital Audio Receiver/Transmitter Digital Transmission Content Protection (DTCP) Memory-to-Memory (MTM) Synchronous/Asynchronous Sample Rate Converter (SRC) Input Data Port (IDP) Precision Clock Generator (PCG) Peripheral Timers I/O Processor Features DMA Controller System Design Program Booting Phase-Locked Loop Power Supplies Target Board JTAG Emulator Connector Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add-Ins for CrossCore Embedded Studio Board Support Packages for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains Pin Function Descriptions Specifications Operating Conditions Electrical Characteristics Package Information ESD Caution Maximum Power Dissipation Absolute Maximum Ratings Timing Specifications Core Clock Requirements Voltage Controlled Oscillator Power-Up Sequencing Clock Input Clock Signals Reset Interrupts Core Timer Timer PWM_OUT Cycle Timing Timer WDTH_CAP Timing DAI Pin to Pin Direct Routing Precision Clock Generator (Direct Pin Routing) Flags Memory Read—Parallel Port Memory Write—Parallel Port Serial Ports Input Data Port (IDP) Parallel Data Acquisition Port (PDAP) Pulse-Width Modulation Generators Sample Rate Converter—Serial Input Port Sample Rate Converter—Serial Output Port S/PDIF Transmitter S/PDIF Transmitter-Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode SPI Interface—Master SPI Interface—Slave JTAG Test Access Port and Emulation Output Drive Currents Test Conditions Capacitive Loading Thermal Characteristics 144-Lead LQFP_EP Pin Configurations 136-Ball BGA Pin Configurations Package Dimensions Surface-Mount Design Automotive Products Ordering Guide