Datasheet ADSP-SC570, ADSP-SC571, ADSP-SC572, ADSP-SC573, ADSP-21571, ADSP-21573 (Analog Devices) - 10

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ADSP-SC570/SC571/SC572/SC573/ADSP-21571/21573 Variable Instruction Set Architecture (VISA)
data sharing, and exclusive data access to enable multiprocessor programming. To enhance the reliability of the application, L1 In addition to supporting the standard 48-bit instructions from data RAMs support parity error detection logic for every byte. previous SHARC processors, the SHARC+ core processors sup- Additionally, the processors detect illegal opcodes. Core inter- port 16-bit and 32-bit opcodes for many instructions, formerly rupts flag both errors. Master ports of the core also detect for 48-bit in the ISA. This feature, called variable instruction set failed external accesses. architecture (VISA), drops redundant or unused bits within the 48-bit instruction to create more efficient and compact code.
SYSTEM INFRASTRUCTURE
The program sequencer supports fetching these 16-bit and 32- bit instructions from both internal and external memories. The following sections describe the system infrastructure of the VISA is not an operating mode; it is only address dependent ADSP-SC57x/ADSP-2157x processors. (refer to memory map ISA/VISA address spaces in Table 7).
System L2 Memory
Furthermore, it allows jumps between ISA and VISA instruc- tion fetches. A system L2 SRAM memory of 8 Mb (1 MB) is available to both SHARC+ cores, the ARM Cortex-A5 core, and the system DMA
Single-Cycle Fetch of Instructional Four Operands
channels (see Table 5). The L2 SRAM block is subdivided into The ADSP-SC57x/ADSP-2157x processors feature an enhanced eight banks to support concurrent access to the L2 memory Harvard architecture in which the DM bus transfers data and ports. Memory accesses to the L2 memory space are multicycle PM bus transfers both instructions and data. accesses by both the ARM Cortex-A5 and SHARC+ cores. With the separate program memory bus, data memory buses, The memory space is used for various situations including and on-chip instruction conflict cache, the processor can simul- • ARM Cortex-A5 to SHARC+ core data sharing and inter- taneously fetch four operands (two over each data bus) and one core communications instruction from the conflict cache, in a single cycle. • Accelerator and peripheral sources and destination mem-
Core Event Controller (CEC)
ory to avoid accessing data in the external memory The SHARC+ core generates various core interrupts (including • A location for DMA descriptors arithmetic and circular buffer instruction flow exceptions) and • Storage for additional data for either the ARM Cortex-A5 SEC events (debug or monitor and software). The core event or SHARC+ cores to avoid external memory latencies and controller (CEC) is used to unmask interrupts for core process- reduce external memory bandwidth ing (enabled in the IMASK register). • Storage for incoming Ethernet traffic to improve
Instruction Conflict Cache
performance The processors include a 32-entry instruction cache that enables • Storage for data coefficient tables cached by the three-bus operation for fetching an instruction and four data SHARC+ core values. The cache is selective—only the instructions that require See System Memory Protection Unit (SMPU) section for fetches conflict with the PM bus data accesses cache. This cache options in limiting access by specific cores and DMA masters. allows full speed execution of core, looped operations, such as The ARM Cortex-A5 core has an L1 instruction and data cache, digital filter multiply accumulates, and FFT butterfly process- each of which is 32 kB in size. The core also has an L2 cache ing. The conflict cache serves for on-chip bus conflicts only. controller of 256 kB. When enabling the caches, accesses to all
Branch Target Buffer (BTB)/Branch Predictor (BP)
other memory spaces (internal and external) go through the cache. Implementation of a hardware-based branch predictor (BP) and branch target buffer (BTB) reduce branch delay. The program
SHARC+ Core L1 Memory in Multiprocessor Space
sequencer supports efficient branching using the BTB for condi- The ARM Cortex-A5 core can access the L1 memory of the tional and unconditional instructions. SHARC+ core. See Table 6 for the L1 memory address in multi-
Addressing Spaces
processor space. The SHARC+ core can access the L1 memory of the other SHARC+ core in the multiprocessor space. In addition to traditionally supported long word, normal word, extended precision word, and short word addressing aliases, the
One Time Programmable Memory (OTP)
processors support byte addressing for the data and instruction The processors feature 7 Kb of one time programmable (OTP) accesses. The enhanced ISA/VISA provides new instructions for memory which is memory map accessible. This memory can be accessing all sizes of data from byte space as well as converting programmed with custom keys and it supports secure boot and word addresses to byte and byte to word addresses. secure operation.
Additional Features I/O Memory Space
The enhanced ISA/VISA of the ADSP-SC57x/ADSP-2157x pro- Mapped I/Os include SPI2 memory address space (see Table 7). cessors provides a memory barrier instruction for data synchronization, exclusive data access support for multicore Rev. B | Page 10 of 142 | June 2018 Document Outline System Features Memory Additional Features Table Of Contents Revision History General Description ARM Cortex-A5 Processor Generic Interrupt Controller (GIC), PL390 (ADSP-SC57x Only) Generic Interrupt Controller Port0 (GICPORT0) Generic Interrupt Controller Port1 (GICPORT1) L2 Cache Controller, PL310 (ADSP-SC57x Only) SHARC Processor L1 Memory L1 Master and Slave Ports L1 On-Chip Memory Bandwidth Instruction and Data Cache System Event Controller (SEC) Input Core Memory-Mapped Registers (CMMR) SHARC+ Core Architecture Single-Instruction, Multiple Data (SIMD) Computational Engine Independent Parallel Computation Units Core Timer Data Register File Context Switch Universal Registers Data Address Generators (DAG) With Zero-Overhead Hardware Circular Buffer Support Flexible Instruction Set Architecture (ISA) Variable Instruction Set Architecture (VISA) Single-Cycle Fetch of Instructional Four Operands Core Event Controller (CEC) Instruction Conflict Cache Branch Target Buffer (BTB)/Branch Predictor (BP) Addressing Spaces Additional Features System Infrastructure System L2 Memory SHARC+ Core L1 Memory in Multiprocessor Space One Time Programmable Memory (OTP) I/O Memory Space System Memory Map System Crossbars (SCBs) Direct Memory Access (DMA) Memory Direct Memory Access (MDMA) Extended Memory DMA Cyclic Redundant Code (CRC) Protection Event Handling System Event Controller (SEC) Trigger Routing Unit (TRU) Security Features ARM TrustZone Cryptographic Hardware Accelerators System Protection Unit (SPU) System Memory Protection Unit (SMPU) Security Features Disclaimer Safety Features Multiparity Bit Protected SHARC+ Core L1 Memories Parity Protected ARM L1 Cache Error Correcting Codes (ECC) Protected L2 Memories Parity-Protected Peripheral Memories Cyclic Redundant Code (CRC) Protected Memories Signal Watchdogs System Event Controller (SEC) Memory Error Controller (MEC) Processor Peripherals Dynamic Memory Controller (DMC) Digital Audio Interface (DAI) Serial Port (SPORT) Asynchronous Sample Rate Converter (ASRC) S/PDIF-Compatible Digital Audio Receiver/Transmitter Precision Clock Generators (PCG) Enhanced Parallel Peripheral Interface (EPPI) Universal Asynchronous Receiver/Transmitter (UART) Ports Serial Peripheral Interface (SPI) Ports Link Port (LP) ADC Control Module (ACM) Interface Ethernet Media Access Controller (EMAC) Audio Video Bridging (AVB) Support Precision Time Protocol (PTP) IEEE 1588 Support Controller Area Network (CAN) Timers General-Purpose (GP) Timers (TIMER) Watchdog Timer (WDT) General-Purpose Counters (CNT) Housekeeping Analog-to-Digital Converter (HADC) USB 2.0 On the Go (OTG) Dual-Role Device Controller (BGA Only) Media Local Bus (MediaLB) 2-Wire Controller Interface (TWI) General-Purpose I/O (GPIO) Pin Interrupts Mobile Storage Interface (MSI) System Acceleration Finite Impulse Response (FIR) Accelerator Infinite Impulse Response (IIR) Accelerator System Design Clock Management Reset Control Unit (RCU) Clock Generation Unit (CGU) System Crystal Oscillator and USB Crystal Oscillator Clock Distribution Unit (CDU) Power-Up Clock Out/External Clock Booting Thermal Monitoring Unit (TMU) Power Supplies Power Management Target Board JTAG Emulator Connector System Debug System Watchpoint Unit (SWU) Debug Access Port (DAP) Development Tools Integrated Development Environments (IDEs) EZ-KIT Lite Evaluation Board EZ-KIT Lite Evaluation Kits Software Add Ins for CrossCore Embedded Studio Board Support Packages (BSPs) for Evaluation Hardware Middleware Packages Algorithmic Modules Designing an Emulator-Compatible DSP Board (Target) Additional Information Related Signal Chains ADSP-SC57x/ADSP-2157x Detailed Signal Descriptions 400-Ball CSP_BGA Signal Descriptions GPIO Multiplexing for 400-Ball CSP_BGA Package 176-Lead LQFP Signal Descriptions GPIO Multiplexing for 176-Lead LQFP Package ADSP-SC57x/ADSP-2157x Designer Quick Reference Specifications Operating Conditions Clock Related Operating Conditions Electrical Characteristics Total Internal Power Dissipation Application Dependent Current Clock Current Current from High Speed Peripheral Operation Data Transmission Current HADC HADC Electrical Characteristics HADC DC Accuracy HADC Timing Specifications TMU TMU Characteristics Absolute Maximum Ratings ESD Caution Timing Specifications Power-Up Reset Timing Clock and Reset Timing DDR2 SDRAM Clock and Control Cycle Timing DDR2 SDRAM Read Cycle Timing DDR2 SDRAM Write Cycle Timing Mobile DDR (LPDDR) SDRAM Clock and Control Cycle Timing Mobile DDR SDRAM Read Cycle Timing Mobile DDR SDRAM Write Cycle Timing DDR3 SDRAM Clock and Control Cycle Timing DDR3 SDRAM Read Cycle Timing DDR3 SDRAM Write Cycle Timing Enhanced Parallel Peripheral Interface (EPPI) Timing Link Ports (LPs) Serial Ports (SPORTs) Asynchronous Sample Rate Converter (ASRC)—Serial Input Port Asynchronous Sample Rate Converter (ASRC)—Serial Output Port SPI Port—Master Timing SPI0, SPI1, and SPI2 SPI Port—Slave Timing SPI0, SPI1, and SPI2 SPI Port—SPIx_RDY Slave Timing SPI Port—Open Drain Mode (ODM) Timing SPI Port—SPIx_RDY Master Timing Precision Clock Generator (PCG) (Direct Pin Routing) General-Purpose IO Port Timing General-Purpose I/O Timer Cycle Timing DAI0 Pin to DAI0 Pin Direct Routing Up/Down Counter/Rotary Encoder Timing ADC Controller Module (ACM) Timing Universal Asynchronous Receiver-Transmitter (UART) Ports—Receive and Transmit Timing Controller Area Network (CAN) Interface Universal Serial Bus (USB) 10/100 EMAC Timing 10/100/1000 EMAC Timing Sony/Philips Digital Interface (S/PDIF) Transmitter S/PDIF Transmitter Serial Input Waveforms S/PDIF Transmitter Input Data Timing Oversampling Clock (TxCLK) Switching Characteristics S/PDIF Receiver Internal Digital PLL Mode MediaLB (MLB) Mobile Storage Interface (MSI) Controller Timing Program Trace Macrocell (PTM) Timing Debug Interface (JTAG Emulation Port) Timing Output Drive Currents Test Conditions Output Enable Time Measurement Output Disable Time Measurement Capacitive Loading Environmental Conditions ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments (Numerical by Ball Number) ADSP-SC57x/ADSP-2157x 400-Ball BGA Ball Assignments (Alphabetical by Pin Name) Configuration of the 400-Ball CSP_BGA ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments (Numerical by Lead Number) ADSP-SC57x/ADSP-2157x 176-Lead LQFP Lead Assignments (Alphabetical by Pin Name) Configuration of the 176-Lead LQFP Lead Configuration Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide