Datasheet AD5116 (Analog Devices) - 4

link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4 link to page 4
AD5116 Data Sheet Parameter Symbol Test Conditions/Comments Min Typ1 Max Unit
POWER SUPPLIES Single-Supply Power Range 2.3 5.5 V Positive Supply Current IDD VDD = 5 V 0.75 3.5 µA VDD = 2.7 V 2.5 µA VDD = 2.3 V 2.4 µA EEMEM Store Current3, 7 IDD_NVM_STORE 2 mA EEMEM Read Current3, 8 IDD_NVM_READ 320 µA Power Dissipation9 PDISS VIH = VLOGIC or VIL = GND 5 µW Power Supply Rejection3 PSR ∆VDD/∆VSS = 5 V ± 10% RAB = 5 kΩ −43 dB RAB =10 kΩ −50 dB RAB = 80 kΩ −64 dB DYNAMIC CHARACTERISTICS3, 10 Bandwidth BW Code = half scale − 3 dB RAB = 5 kΩ 4 MHz RAB = 10 kΩ 2 MHz RAB = 80 kΩ 200 kHz Total Harmonic Distortion THD VA = VDD/2 + 1 V rms, VB = VDD/2, f = 1 kHz, code = half scale RAB = 5 kΩ −75 dB RAB = 10 kΩ −80 dB RAB = 80 kΩ −85 dB VW Settling Time ts VA = 5 V, VB = 0 V, ±0.5 LSB error band RAB = 5 kΩ 2.5 µs RAB = 10 kΩ 3 µs RAB = 80 kΩ 10 µs Resistor Noise Density eN_WB Code = half scale, TA = 25°C, f = 100 kHz RAB = 5 kΩ 7 nV/√Hz RAB = 10 kΩ 9 nV/√Hz RAB = 80 kΩ 20 nV/√Hz FLASH/EE MEMORY RELIABILITY3 Endurance11 TA = 25°C 1 MCycles 100 kCycles Data Retention12 50 Years 1 Typical values represent average readings at 25°C, VDD = 5 V, VSS = 0 V, and VLOGIC = 5 V. 2 Resistor position nonlinearity error (R-INL) is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper positions. R-DNL measures the relative step change from ideal between successive tap positions. The maximum wiper current is limited to 0.8 × VDD/RAB. 3 Guaranteed by design and characterization, not subject to production test. 4 INL and DNL are measured at VWB with the RDAC configured as a potentiometer divider similar to a voltage output DAC. VA = VDD and VB = 0 V. DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. 5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other. 6 CA is measured with VW = VA = 2.5 V, CB is measured with VW = VB = 2.5 V, and CW is measured with VA = VB = 2.5 V. 7 Different from operating current; supply current for NVM program lasts approximately 30 ms. 8 Different from operating current; supply current for NVM read lasts approximately 20 µs. 9 PDISS is calculated from (IDD × VDD). 10 All dynamic characteristics use VDD = 5.5 V, and VLOGIC = 5 V. 11 Endurance is qualified at 100,000 cycles per JEDEC Standard 22, Method A117 and measured at 150°C. 12 Retention lifetime equivalent at junction temperature (TJ) = 125°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 1 eV derates with junction temperature in the Flash/EE memory. Rev. B | Page 4 of 16 Document Outline Features Applications Functional Block Diagram General Description Revision History Specifications Electrical Characteristics Interface Timing Specifications Timing Diagrams Absolute Maximum Ratings Thermal Resistance ESD Caution Pin Configuration and Function Descriptions Typical Performance Characteristics Test Circuits Theory of Operation RDAC Register Manual Increment Auto Scan Increment Low Wiper Resistance Feature EEPROM Automatic Save Enable Auto Save Manual Store End Scale Resistance Indicator RDAC Architecture Top Scale/Bottom Scale Architecture Programming the Variable Resistor Rheostat Operation—±8% Resistor Tolerance Programming the Potentiometer Divider Voltage Output Operation Terminal Voltage Operating Range Power-Up Sequence Layout and Power Supply Biasing Outline Dimensions Ordering Guide