Datasheet BridgeSwitch Family (Power Integrations) - 10

BridgeSwitch
In case the SM pin current exceeds I for at least t (typical y 80 ms), OV D(OV) High-Voltage BridgeSwitch terminates the current low-side or high-side power Bus FREDFET on-time and reports the fault to the system MCU through the FAULT pin. It ignores any subsequent FREDFET turn-on signals received at either INL or /INH until the SM pin current has dropped by at least I for the duration of t . The FAULT pin reports a status OV(HYST) D(OV) RHV1 update once the high-voltage bus overvoltage condition has cleared. The system MCU may decide to stop sending turn-on signals to other BridgeSwitch devices in the inverter until the bus OV fault condition has
SM
cleared and the bus sensing device provided a status update accord- Bus tD(OV) FAULT ingly. A full power-up sequence is recommended after the bus OV fault UV/OV Logic clears. High-side BYPASS capacitors may have discharged due to the Sense tD(UV) disabled low-side FREDFET switching during the bus OV fault. Table 3 lists exemplary high-voltage bus monitoring thresholds with three different sensing resistor R values. HV1
SG
PI-8302-040517
6 M
Ω
7 M
Ω
8 M
Ω
Sensing Resistor RHV1
Figure 15. High-Voltage Bus Monitoring with SYSTEM MONITOR Pin.
Bus Voltage UV or OV Threshold
The bus voltage sensing circuitry has five distinct current thresholds as IOV (typical y 60 mA) 362 V 422 V 482 V shown in Figure 16. Thresholds I , I , I , and I are used to UV55 UV70 UV85 UV100 IUV100 (typical y 35 mA) 212 V 247 V 282 V detect high-voltage bus undervoltage conditions. Threshold I is used OV to detect a high-voltage bus overvoltage condition. The device reports IUV85 (typical y 30 mA) 182 V 212 V 242 V a high-voltage bus fault through the STATUS COMMUNICATION pin I anytime the current into the SM pin either drops below one of the four UV70 (typical y 25 mA) 152 V 177 V 202 V undervoltage thresholds or if it exceeds the overvoltage threshold (see IUV55 (typical y 20 mA) 122 V 142 V 162 V Table 4 for details). Table 3. Effective High-Voltage Bus Monitoring Thresholds. Using multiple sense resistors with different values on more than one device increases the bus voltage sensing granularity further. Overvolt- age protection can be disabled by limiting the current into the SM pin to less than the I threshold through Zener diode V and resistor R as OV R1 HV2 shown in Figure 18. Bus undervoltage sensing remains active in this configuration. IOV(HYST) Adding a smal capacitor (maximum 100 pF) to the SM pin can improve bus monitoring accuracy in noisy environments. I ISM OV I I I I
System Level Temperature Monitoring
UV55UV70UV85UV100 The SYSTEM MONITOR pin enables monitoring the temperature of an PI-8303-032817 external component through an NTC thermistor as shown in Figure 17. Resistor R al ows fine-tuning the actual over-temperature threshold to 2 Figure 16. System Monitor Input Current Thresholds. the desired level with a given NTC resistor. An undervoltage condition has to be present for at least t (typical y Current source I (typical y 96 mA) periodical y injects a current into the D(UV) TM 40 ms) before it is reported to the system MCU. The device also NTC thermistor R . Its resistance fal s with the temperature rising. NTC communicates if a given undervoltage condition clears for at least t . Once the voltage level at the SM pin drops below V (typical y 1.2 V), D(UV) TH(TM) the detected system level over-temperature fault is communicated Note, during a bus brown-out condition, the device will report for through the FAULT-pin after delay timer t expires (see Table 4 for instance a UV 70% status update if the bus voltage fal s below 177 V for D(TM) details). The resistance of thermistor R at the desired system at least t with a 7 MΩ sensing resistance (refer to Tables 3 and 4). NTC(TSYS) D(UV) over-temperature threshold T determines R : If in this example the bus voltage recovers and rises above 177 V for at SYS 2 least t , the UV 70% condition clears and the device will report a UV D(UV) R2 = 12.5 kX - RNTC^TSYSh 85% status update.
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Rev. F 11/18 www.power.com Document Outline Product Highlights Description Output Power Table Pin Functional Description BridgeSwitch Functional Description Application Example PCB Design Guidelines Absolute Maximum Ratings Thermal Resistance Key Electrical Characteristics Typical Performance Characteristics inSOP-24C Package Drawing Package Marking Part Ordering and MSL Table ESD and Latch-Up Table Part Ordering Information