Datasheet LT1175 (Analog Devices) - 8

LT1175
PIN FUNCTIONS (N8/Q/ST/S8/T) VIN (Pins 1, 8/Pin 3, Tab/Pin 2, Tab/Pins 1, 8/Pin 3, Tab):
3.8V at the SENSE pin. Input bias current is typically 75nA Power is supplied to the device through this pin. A bypass fl owing out of the pin. Maximum forced voltage on the capacitor is required on this pin if the device is more than SENSE pin is 2V and –10V with respect to GND pin. six inches away from the main fi lter capacitor. In general, The fi xed 5V version utilizes the SENSE pin to give true the impedance of a battery rises with frequency, so it is Kelvin connections to the load or to drive an external pass advisable to include a bypass capacitor in battery-powered transistor for higher output currents. Bias current out circuits. A 1μF or larger tantalum capacitor is suggested of the 5V SENSE pin is approximately 12μA. Separating for all applications, but if low ESR capacitors such as the SENSE and OUTPUT pins also allows for a new loop ceramic or fi lm are used for the output and input capaci- compensation technique described in the Applications tors, the input capacitor should be three times the value Information section. of the output capacitor.
GND (Pin 5/Pin 4/Pin 3/Pin 5/Pin 4):
The GND pin has a
ILIM2, ILIM4 (Pins 2, 7/NA/NA/Pins 2, 7/NA):
The two quiescent current of 45μA at zero load current, increas- current limit pins are emitter sections of the power transis- ing by approximately 10μA per mA of output current. At tor. When left open, they fl oat several hundred millivolts 500mA output current, GND pin current is about 5mA. above the negative input voltage. When shorted to the Current fl ows into the GND pin. input voltage, they increase current limit by a minimum of 200mA for I
SHDN (Pin 6/Pin 5/NA/Pin 6/Pin 5):
The SHDN pin is LIM2 and 400mA for ILIM4. These pins must be connected only to the input voltage, either directly or specially confi gured to allow it to be driven from either through a resistor. positive voltage logic or with negative only logic. Forc- ing the SHDN pin 2V either above or below the GND
OUTPUT (Pin 3/Pin 1/Pin 1/Pin 3/Pin 1):
The OUTPUT pin pin will turn the regulator on. This makes it simple to is the collector of the NPN power transistor. It can be forced connect directly to positive logic signals for active low to the input voltage, to ground or up to 2V positive with shutdown. If no positive voltages are available, the respect to ground without damage or latchup (see Output SHDN pin can be driven below the GND pin to turn the Voltage Reversal in Applications Information section). The regulator on. When left open, the SHDN pin will default LT1175 has foldback current limit, so maximum current at low to a regulator “on” condition. For all voltages below the OUTPUT pin is a function of input-to-output voltage. absolute maximum ratings, the SHDN pin draws only a See Typical Performance Characteristics. few microamperes of current (see Typical Performance
SENSE (Pin 4/Pin 2/NA/Pin 4/Pin 2):
The SENSE pin is Characteristics). Maximum voltage on the SHDN pin is 15V, used in the adjustable version to allow custom selection – 20V with respect to the GND pin and 35V, –5V with of output voltage, with an external divider set to generate respect to the negative input pin. 1175ff 8