Datasheet ADP7185 (Analog Devices) - 6
| Fabricante | Analog Devices |
| Descripción | -500 mA, Ultralow Noise, High PSRR, Low Dropout Linear Regulator |
| Páginas / Página | 19 / 6 — ADP7185. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. VOUT 1. … |
| Formato / tamaño de archivo | PDF / 855 Kb |
| Idioma del documento | Inglés |
ADP7185. Data Sheet. PIN CONFIGURATION AND FUNCTION DESCRIPTIONS. VOUT 1. 8 VIN. SENSE 2. 7 VREG. VA 3. TOP VIEW. 6 GND. (Not to Scale)
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ADP7185 Data Sheet PIN CONFIGURATION AND FUNCTION DESCRIPTIONS VOUT 1 8 VIN SENSE 2 7 VREG ADP7185 VA 3 TOP VIEW 6 GND (Not to Scale) VAFB 4 5 EN NOTES 1. EXPOSED PAD. THE EXPOSED PAD ENHANCES THE THERMAL PERFORMANCE AND IS ELECTRICALLY CONNECTED TO VIN INSIDE THE PACKAGE. IT IS
03 0
RECOMMENDED THAT THE EXPOSED PAD CONNECT
2-
TO THE INPUT VOLTAGE PLANE ON THE BOARD.
93 13 Figure 3. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 4.7 μF or greater capacitor. 2 SENSE Sense Input. Connect this pin to VOUT. 3 VA Low Noise Reference Voltage. Connect a 1 μF capacitor to GND to reduce noise. Do not connect a load to ground. 4 VAFB Output Voltage Reference Feedback (Adjust Mode). Connect a 1 nF to 1 μF capacitor between the VAFB pin and the VA pin to reduce noise. Start-up time is increased as a function of the capacitance. Connect an external resistor divider between the VA pin and the VAFB pin to set the output voltage in adjust mode. 5 EN Enable. Drive EN at least +1.25 V above or −1.3 V below ground to enable the regulator or drive EN to ground to turn the regulator off. For automatic startup, connect EN to VIN. 6 GND Ground. 7 VREG Regulated Input Supply to the LDO Amplifier. Bypass VREG to GND with a 1 μF or greater capacitor. Do not connect a load to ground. 8 VIN Regulator Input Supply. Bypass VIN to GND with a 4.7 μF or greater capacitor. EP Exposed pad. The exposed pad enhances the thermal performance and is electrically connected to VIN inside the package. It is recommended that the exposed pad connect to the input voltage plane on the board. Rev. 0 | Page 6 of 19 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ADJUSTABLE MODE OPERATION ENABLE PIN OPERATION START-UP TIME APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor CA and CAFB Capacitors Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT (UVLO) CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE
03 0
RECOMMENDED THAT THE EXPOSED PAD CONNECT
2-
TO THE INPUT VOLTAGE PLANE ON THE BOARD.
93 13 Figure 3. Pin Configuration
Table 5. Pin Function Descriptions Pin No. Mnemonic Description
1 VOUT Regulated Output Voltage. Bypass VOUT to GND with a 4.7 μF or greater capacitor. 2 SENSE Sense Input. Connect this pin to VOUT. 3 VA Low Noise Reference Voltage. Connect a 1 μF capacitor to GND to reduce noise. Do not connect a load to ground. 4 VAFB Output Voltage Reference Feedback (Adjust Mode). Connect a 1 nF to 1 μF capacitor between the VAFB pin and the VA pin to reduce noise. Start-up time is increased as a function of the capacitance. Connect an external resistor divider between the VA pin and the VAFB pin to set the output voltage in adjust mode. 5 EN Enable. Drive EN at least +1.25 V above or −1.3 V below ground to enable the regulator or drive EN to ground to turn the regulator off. For automatic startup, connect EN to VIN. 6 GND Ground. 7 VREG Regulated Input Supply to the LDO Amplifier. Bypass VREG to GND with a 1 μF or greater capacitor. Do not connect a load to ground. 8 VIN Regulator Input Supply. Bypass VIN to GND with a 4.7 μF or greater capacitor. EP Exposed pad. The exposed pad enhances the thermal performance and is electrically connected to VIN inside the package. It is recommended that the exposed pad connect to the input voltage plane on the board. Rev. 0 | Page 6 of 19 Document Outline FEATURES APPLICATIONS TYPICAL APPLICATION CIRCUITS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY SPECIFICATIONS INPUT AND OUTPUT CAPACITOR RECOMMENDED SPECIFICATIONS ABSOLUTE MAXIMUM RATINGS THERMAL DATA THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS THEORY OF OPERATION ADJUSTABLE MODE OPERATION ENABLE PIN OPERATION START-UP TIME APPLICATIONS INFORMATION ADIsimPOWER DESIGN TOOL CAPACITOR SELECTION Output Capacitor Input Bypass Capacitor CA and CAFB Capacitors Input and Output Capacitor Properties UNDERVOLTAGE LOCKOUT (UVLO) CURRENT-LIMIT AND THERMAL OVERLOAD PROTECTION THERMAL CONSIDERATIONS OUTLINE DIMENSIONS ORDERING GUIDE