Datasheet LTC2333-18 (Analog Devices) - 8
| Fabricante | Analog Devices |
| Descripción | Buffered 8-Channel, 18-Bit, 800ksps Differential ±10.24V ADC with 30VP-P Common Mode Range |
| Páginas / Página | 40 / 8 — ADC TIMING CHARACTERISTICS Note 1:. Note 11:. Note 12:. Note 2:. Note 3:. … |
| Formato / tamaño de archivo | PDF / 2.2 Mb |
| Idioma del documento | Inglés |
ADC TIMING CHARACTERISTICS Note 1:. Note 11:. Note 12:. Note 2:. Note 3:. Note 4:. Note 5:. Note 13:. Note 6:. Note 14:. Note 7:. Note 8:
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LTC2333-18
ADC TIMING CHARACTERISTICS Note 1:
Stresses beyond those listed under Absolute Maximum Ratings straight line passing through the actual endpoints of the transfer curve. may cause permanent damage to the device. Exposure to any Absolute The deviation is measured from the center of the quantization band. Maximum Rating condition for extended periods may affect device
Note 11:
Guaranteed by design, not subject to test. reliability and lifetime.
Note 12:
For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is
Note 2:
All voltage values are with respect to GND. the offset voltage measured from –0.5LSB when the output code flickers
Note 3:
VDDLBYP is the output of an internal voltage regulator, and should between 00 0000 0000 0000 0000 and 11 1111 1111 1111 1111. Full- only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND, scale error for these SoftSpan ranges is the worst-case deviation of the as described in the Pin Functions section. Do not connect this pin to any first and last code transitions from ideal and includes the effect of offset external circuitry. error. For unipolar SoftSpan ranges 5, 4, 1, and 0, zero-scale error is
Note 4:
When these pin voltages are taken below V the offset voltage measured from 0.5LSB when the output code flickers EE or above VCC, they will be clamped by internal diodes. This product can handle input currents between 00 0000 0000 0000 0000 and 00 0000 0000 0000 0001. Full- of up to 100mA below V scale error for these SoftSpan ranges is the worst-case deviation of the EE or above VCC without latch-up.
Note 5:
When these pin voltages are taken below GND or above V last code transition from ideal and includes the effect of offset error. DD or OV
Note 13:
All specifications in dB are referred to a full-scale input in the DD, they will be clamped by internal diodes. This product can handle currents of up to 100mA below GND or above V relevant SoftSpan input range, except for crosstalk, which is referred to DD or OVDD without latch-up.
Note 6:
–16.5V ≤ V the crosstalk injection signal amplitude. EE ≤ 0V, 7.5V ≤ VCC ≤ 38V, 10V ≤ (VCC – VEE) ≤ 38V, V
Note 14:
Temperature coefficient is calculated by dividing the maximum DD = 5V, unless otherwise specified.
Note 7:
Recommended operating conditions. change in output voltage by the specified temperature range.
Note 8:
Exceeding these limits on any channel may corrupt conversion
Note 15:
When REFBUF is overdriven, the internal reference buffer must results on other channels. Driving an analog input above V be disabled by setting REFIN = 0V. CC on any channel up to 10mA will not affect conversion results on other channels.
Note 16:
IREFBUF varies proportionally with sample rate. Driving an analog input below VEE may corrupt conversion results on other
Note 17:
Analog input buffer supply currents from IVCC and IVEE are channels. Refer to Applications Information section for further details. reduced outside the acquisition period. Refer to nap mode in Applications Refer to Absolute Maximum Ratings section for pin voltage limits related Information section. to device reliability.
Note 18:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V,
Note 9:
VCC = 15V, VEE = –15V, VDD = 5V, OVDD = 2.5V, fSMPL = 800ksps, and OVDD = 5.25V. internal reference and buffer, true bipolar input signal drive in bipolar
Note 19:
A tSCKI period of 10ns minimum allows a shift clock frequency of SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless up to 100MHz for rising edge capture. otherwise specified.
Note 20:
VICM = 1.2V, VID = 350mV for LVDS differential input pairs.
Note 10:
Integral nonlinearity is defined as the deviation of a code from a
CMOS Timing
0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 233318 F01a 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
LVDS Timing (Differential)
+200mV tWIDTH –200mV t tDELAY 0V 0V DELAY 233318 F01b +200mV +200mV –200mV –200mV
Figure 1. Voltage Levels for Timing Specifications
233318f 8 For more information www.linear.com/LTC2333-18
ADC TIMING CHARACTERISTICS Note 1:
Stresses beyond those listed under Absolute Maximum Ratings straight line passing through the actual endpoints of the transfer curve. may cause permanent damage to the device. Exposure to any Absolute The deviation is measured from the center of the quantization band. Maximum Rating condition for extended periods may affect device
Note 11:
Guaranteed by design, not subject to test. reliability and lifetime.
Note 12:
For bipolar SoftSpan ranges 7, 6, 3, and 2, zero-scale error is
Note 2:
All voltage values are with respect to GND. the offset voltage measured from –0.5LSB when the output code flickers
Note 3:
VDDLBYP is the output of an internal voltage regulator, and should between 00 0000 0000 0000 0000 and 11 1111 1111 1111 1111. Full- only be connected to a 2.2μF ceramic capacitor to bypass the pin to GND, scale error for these SoftSpan ranges is the worst-case deviation of the as described in the Pin Functions section. Do not connect this pin to any first and last code transitions from ideal and includes the effect of offset external circuitry. error. For unipolar SoftSpan ranges 5, 4, 1, and 0, zero-scale error is
Note 4:
When these pin voltages are taken below V the offset voltage measured from 0.5LSB when the output code flickers EE or above VCC, they will be clamped by internal diodes. This product can handle input currents between 00 0000 0000 0000 0000 and 00 0000 0000 0000 0001. Full- of up to 100mA below V scale error for these SoftSpan ranges is the worst-case deviation of the EE or above VCC without latch-up.
Note 5:
When these pin voltages are taken below GND or above V last code transition from ideal and includes the effect of offset error. DD or OV
Note 13:
All specifications in dB are referred to a full-scale input in the DD, they will be clamped by internal diodes. This product can handle currents of up to 100mA below GND or above V relevant SoftSpan input range, except for crosstalk, which is referred to DD or OVDD without latch-up.
Note 6:
–16.5V ≤ V the crosstalk injection signal amplitude. EE ≤ 0V, 7.5V ≤ VCC ≤ 38V, 10V ≤ (VCC – VEE) ≤ 38V, V
Note 14:
Temperature coefficient is calculated by dividing the maximum DD = 5V, unless otherwise specified.
Note 7:
Recommended operating conditions. change in output voltage by the specified temperature range.
Note 8:
Exceeding these limits on any channel may corrupt conversion
Note 15:
When REFBUF is overdriven, the internal reference buffer must results on other channels. Driving an analog input above V be disabled by setting REFIN = 0V. CC on any channel up to 10mA will not affect conversion results on other channels.
Note 16:
IREFBUF varies proportionally with sample rate. Driving an analog input below VEE may corrupt conversion results on other
Note 17:
Analog input buffer supply currents from IVCC and IVEE are channels. Refer to Applications Information section for further details. reduced outside the acquisition period. Refer to nap mode in Applications Refer to Absolute Maximum Ratings section for pin voltage limits related Information section. to device reliability.
Note 18:
Parameter tested and guaranteed at OVDD = 1.71V, OVDD = 2.5V,
Note 9:
VCC = 15V, VEE = –15V, VDD = 5V, OVDD = 2.5V, fSMPL = 800ksps, and OVDD = 5.25V. internal reference and buffer, true bipolar input signal drive in bipolar
Note 19:
A tSCKI period of 10ns minimum allows a shift clock frequency of SoftSpan ranges, unipolar signal drive in unipolar SoftSpan ranges, unless up to 100MHz for rising edge capture. otherwise specified.
Note 20:
VICM = 1.2V, VID = 350mV for LVDS differential input pairs.
Note 10:
Integral nonlinearity is defined as the deviation of a code from a
CMOS Timing
0.8 • OVDD tWIDTH 0.2 • OVDD t tDELAY 50% 50% DELAY 233318 F01a 0.8 • OVDD 0.8 • OVDD 0.2 • OVDD 0.2 • OVDD
LVDS Timing (Differential)
+200mV tWIDTH –200mV t tDELAY 0V 0V DELAY 233318 F01b +200mV +200mV –200mV –200mV
Figure 1. Voltage Levels for Timing Specifications
233318f 8 For more information www.linear.com/LTC2333-18