Datasheet AD4112 (Analog Devices) - 8

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AD4112 Data Sheet TIMING CHARACTERISTICS
IOVDD = 2 V to 5.5 V, DGND = 0 V, Input Logic 0 = 0 V, Input Logic 1 = IOVDD, capacitive load (CLOAD) = 20 pF, unless otherwise noted.
Table 2. Parameter Limit at TMIN, TMAX Unit Description1, 2
SCLK t3 25 ns min SCLK high pulse width t4 25 ns min SCLK low pulse width READ OPERATION t1 0 ns min CS falling edge to DOUT/RDY active time 15 ns max IOVDD = 4.75 V to 5.5 V 40 ns max IOVDD = 2 V to 3.6 V t 3 2 0 ns min SCLK active edge to data valid delay4 12.5 ns max IOVDD = 4.75 V to 5.5 V 25 ns max IOVDD = 2 V to 3.6 V t 5 5 2.5 ns min Bus relinquish time after CS inactive edge 20 ns max t6 0 ns min SCLK inactive edge to CS inactive edge t7 10 ns min SCLK inactive edge to DOUT/RDY high/low WRITE OPERATION t8 0 ns min CS falling edge to SCLK active edge setup time4 t9 8 ns min Data valid to SCLK edge setup time t10 8 ns min Data valid to SCLK edge hold time t11 5 ns min CS rising edge to SCLK edge hold time 1 Sample tested during initial release to ensure compliance. 2 See Figure 2 and Figure 3. 3 This parameter is defined as the time required for the output to cross the VOL or VOH limits. 4 The SCLK active edge is the falling edge of SCLK. 5 DOUT/RDY returns high after a read of the data register. In single-conversion mode and continuous conversion mode, the same data can be read again, if required, while DOUT/RDY is high. However, care must be taken to ensure that subsequent reads do not occur close to the next output update. If the continuous read feature is enabled, the digital word can be read only once. Rev. 0 | Page 8 of 58 Document Outline FEATURES APPLICATIONS GENERAL DESCRIPTION TABLE OF CONTENTS REVISION HISTORY FUNCTIONAL BLOCK DIAGRAM SPECIFICATIONS TIMING CHARACTERISTICS Timing Diagrams ABSOLUTE MAXIMUM RATINGS THERMAL RESISTANCE ESD CAUTION PIN CONFIGURATION AND FUNCTION DESCRIPTIONS TYPICAL PERFORMANCE CHARACTERISTICS NOISE PERFORMANCE AND RESOLUTION THEORY OF OPERATION POWER SUPPLIES Single-Supply Operation (AVSS = DGND) DIGITAL COMMUNICATION AD4112 RESET CONFIGURATION OVERVIEW Channel Configuration Channel Registers ADC Setups Setup Configuration Registers Filter Configuration Registers Gain Registers Offset Registers ADC Mode and Interface Mode Configuration ADC Mode Register Interface Mode Register CIRCUIT DESCRIPTION MULTIPLEXER CURRENT INPUTS VOLTAGE INPUTS Fully Differential Inputs Single-Ended Inputs Adjusting Voltage Input Gain AD4112 REFERENCE Internal Reference External Reference BUFFERED REFERENCE INPUT CLOCK SOURCE Internal Oscillator External Crystal External Clock DIGITAL FILTER SINC5 + SINC1 FILTER SINC3 FILTER SINGLE CYCLE SETTLING ENHANCED 50 Hz AND 60 Hz REJECTION FILTERS OPERATING MODES CONTINUOUS CONVERSION MODE CONTINUOUS READ MODE SINGLE CONVERSION MODE STANDBY AND POWER-DOWN MODES CALIBRATION DIGITAL INTERFACE CHECKSUM PROTECTION CRC CALCULATION Polynomial Example of a Polynomial CRC Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) XOR Calculation Example of an XOR Calculation—24-Bit Word: 0x654321 (Eight Command Bits and 16-Bit Data) INTEGRATED FUNCTIONS GENERAL-PURPOSE OUPUTS DELAY 16-BIT/24-BIT CONVERSIONS DOUT_RESET SYNCHRONIZATION Normal Synchronization Alternate Synchronization ERROR FLAGS ADC_ERROR CRC_ERROR REG_ERROR ERRORB Input/Output DATA_STAT IOSTRENGTH INTERNAL TEMPERATURE SENSOR APPLICATIONS INFORMATION GROUNDING AND LAYOUT REGISTER SUMMARY REGISTER DETAILS COMMUNICATIONS REGISTER STATUS REGISTER ADC MODE REGISTER INTERFACE MODE REGISTER REGISTER CHECK DATA REGISTER GPIO CONFIGURATION REGISTER ID REGISTER CHANNEL REGISTER 0 CHANNEL REGISTER 1 TO CHANNEL REGISTER 15 SETUP CONFIGURATION REGISTER 0 SETUP CONFIGURATION REGISTER 1 TO SETUP CONFIGURATION REGISTER 7 FILTER CONFIGURATION REGISTER 0 FILTER CONFIGURATION REGISTER 1 TO FILTER CONFIGURATION REGISTER 7 OFFSET REGISTER 0 OFFSET REGISTER 1 TO OFFSET REGISTER 7 GAIN REGISTER 0 GAIN REGISTER 1 TO GAIN REGISTER 7 OUTLINE DIMENSIONS ORDERING GUIDE