link to page 1 link to page 1 link to page 1 link to page 1 link to page 2 link to page 3 link to page 3 link to page 3 link to page 4 link to page 5 link to page 5 link to page 6 link to page 12 link to page 12 link to page 12 link to page 12 link to page 12 link to page 13 link to page 15 link to page 15 link to page 17 link to page 18 link to page 26 link to page 34 link to page 35 link to page 36 Single Phase, Isolated, Power Monitoring ICACS71020 with Voltage Zero Crossing and Overcurrent DetectionFUNCTIONAL BLOCK DIAGRAM VCC DIGITAL SYSTEM Bandgap R Reference Temperature SDA / MISO To All Temperature I2C/SPI Compensation Sensor Subcircuits Communication Logic SCL / SCLK EEPROM + DIO_0 / MOSI VINP V Charge Pump ADC DIO_1 / CS VINN 2R I ADC IP+ Metrology Engine Fault Logic Hall Sensor Array GND IP– Table of Contents Features and Benefits ... 1 ADCs .. 12 Description .. 1 Raw Signal Sensitivity and Offset Trim ... 12 Package ... 1 Phase Compensation .. 12 Typical Application .. 1 Zero Crossing ... 12 Selection Guide ... 2 Power Calculations ... 13 Absolute Maximum Ratings ... 3 Digital Communication .. 15 Isolation Characteristics .. 3 Registers and EEPROM .. 15 Thermal Characteristics .. 3 EEPROM Error Checking and Correction (ECC) ... 17 Functional Block Diagram ... 4 Memory Map .. 18 Pinout Diagram and Terminal List ... 5 Volatile Memory Map ... 26 Digital I/O .. 5 Application Connections .. 34 Electrical Characteristics ... 6 Recommended PCB Layout .. 35 Data Acquisition ... 12 Package Outline Drawing .. 36 Allegro MicroSystems, LLC 4 955 Perimeter Road Manchester, NH 03103-3353 U.S.A. www.allegromicro.com Document Outline Features and Benefits Description Package Typical Application Selection Guide Absolute Maximum Ratings Isolation Characteristics Thermal Characteristics Functional Block Diagram Pinout Diagram and Terminal List Digital I/O Electrical Characteristics Data Acquisition ADCs Raw Signal Sensitivity and Offset Trim Phase Compensation Zero Crossing Power Calculations Digital Communication Registers and EEPROM EEPROM Error Checking and Correction (ECC) Memory Map Volatile Memory Map Application Connections Recommended PCB Layout Package Outline Drawing