Datasheet ADSP-BF561 (Analog Devices) - 4

link to page 5 ADSP-BF561
ADDRESS ARITHMETIC UNIT SP I3 L3 B3 M3 FP I2 L2 B2 M2 P5 I1 L1 B1 M1 DAG1 P4 I0 L0 B0 M0 P3 DAG0 P2 DA1 32 P1 DA0 32 P0 Y 32 32 PREG RAB O MEMOR T SD 32 LD1 32 ASTAT 32 LD0 32 32 SEQUENCER R7.H R7.L R6.H R6.L R5.H R5.L ALIGN 16 16 R4.H R4.L 8 8 8 8 R3.H R3.L DECODE R2.H R2.L R1.H R1.L BARREL R0.H R0.L SHIFTER 40 40 LOOP BUFFER 40 40 A0 A1 CONTROL UNIT 32 32 DATA ARITHMETIC UNIT
Figure 2. Blackfin Processor Core
MEMORY ARCHITECTURE Internal (On-Chip) Memory
The ADSP-BF561 views memory as a single unified 4G byte The ADSP-BF561 has four blocks of on-chip memory providing address space, using 32-bit addresses. All resources including high bandwidth access to the core. internal memory, external memory, and I/O control registers The first is the L1 instruction memory of each Blackfin core occupy separate sections of this common address space. The consisting of 16K bytes of four-way set-associative cache mem­ memory portions of this address space are arranged in a hierar­ ory and 16K bytes of SRAM. The cache memory may also be chical structure to provide a good cost/performance balance of configured as an SRAM. This memory is accessed at full proces­ some very fast, low latency memory as cache or SRAM very sor speed. When configured as SRAM, each of the two 16K close to the processor, and larger, lower cost and performance banks of memory is broken into 4K sub-banks which can be memory systems farther away from the processor. The independently accessed by the processor and DMA. ADSP-BF561 memory map is shown in Figure 3. The second on-chip memory block is the L1 data memory of The L1 memory system in each core is the highest performance each Blackfin core which consists of four banks of 16K bytes memory available to each Blackfin core. The L2 memory pro­ each. Two of the L1 data memory banks can be configured as vides additional capacity with lower performance. Lastly, the one way of a two-way set-associative cache or as an SRAM. The off-chip memory system, accessed through the External Bus other two banks are configured as SRAM. All banks are accessed Interface Unit (EBIU), provides expansion with SDRAM, flash at full processor speed. When configured as SRAM, each of the memory, and SRAM, optionally accessing more than four 16K banks of memory is broken into 4K sub-banks which 768M bytes of physical memory. The memory DMA controllers can be independently accessed by the processor and DMA. provide high bandwidth data movement capability. They can perform block transfers of code or data between the internal The third memory block associated with each core is a 4K byte L1/L2 memories and the external memory spaces. scratchpad SRAM which runs at the same speed as the L1 mem­ ories, but is only accessible as data SRAM (it cannot be configured as cache memory and is not accessible via DMA). Rev. E | Page 4 of 64 | September 2009 Document Outline Features Peripherals Table of Contents Revision History General Description Portable Low Power Architecture Blackfin Processor Core Memory Architecture Internal (On-Chip) Memory External (Off-Chip) Memory I/O Memory Space Booting Event Handling Core Event Controller (CEC) System Interrupt Controller (SIC) Event Control DMA Controllers Watchdog Timer Timers Serial Ports (SPORTs) Serial Peripheral Interface (SPI) Port UART Port Programmable Flags (PFx) Parallel Peripheral Interface General-Purpose Mode Descriptions Input Mode Frame Capture Mode Output Mode ITU-R 656 Mode Descriptions Active Video Only Mode Vertical Blanking Interval Mode Entire Field Mode Dynamic Power Management Full-On Operating Mode-Maximum Performance Active Operating Mode-Moderate Power Savings Sleep Operating Mode-High Dynamic Power Savings Deep Sleep Operating Mode-Maximum Dynamic Power Savings Hibernate State-Maximum Static Power Savings Power Savings Voltage Regulation Voltage Regulator Layout Guidelines Clock Signals Booting Modes Instruction Set Description Development Tools EZ-KIT Lite Evaluation Board Designing an Emulator-Compatible Processor Board Related Documents Pin Descriptions Specifications Operating Conditions Electrical Characteristics Absolute Maximum Ratings Package Information ESD Sensitivity Timing Specifications Clock and Reset Timing Asynchronous Memory Read Cycle Timing Asynchronous Memory Write Cycle Timing SDRAM Interface Timing External Port Bus Request and Grant Cycle Timing Parallel Peripheral Interface Timing Serial Ports Serial Peripheral Interface (SPI) Port- Master Timing Serial Peripheral Interface (SPI) Port- Slave Timing Universal Asynchronous Receiver Transmitter (UART) Port-Receive and Transmit Timing Programmable Flags Cycle Timing Timer Cycle Timing JTAG Test and Emulation Port Timing Output Drive Currents Power Dissipation Test Conditions Output Enable Time Measurement Output Disable Time Measurement Example System Hold Time Calculation Capacitive Loading Environmental Conditions 256-Ball CSP_BGA (17 mm) Ball Assignment 256-Ball CSP_BGA (12 mm) Ball Assignment 297-Ball PBGA Ball Assignment Outline Dimensions Surface-Mount Design Automotive Products Ordering Guide